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Avoid duplicating logic on frame register selecting when lowering eh_return
No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11052,21 +11052,23 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
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SDValue Handler = Op.getOperand(2);
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DebugLoc dl = Op.getDebugLoc();
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SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
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Subtarget->is64Bit() ? X86::RBP : X86::EBP,
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getPointerTy());
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unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
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EVT PtrVT = getPointerTy();
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unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
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assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
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(FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
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"Invalid Frame Register!");
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SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
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unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
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SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
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SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
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DAG.getIntPtrConstant(RegInfo->getSlotSize()));
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StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
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StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
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Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
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false, false, 0);
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Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
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return DAG.getNode(X86ISD::EH_RETURN, dl,
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MVT::Other,
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Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
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return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
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DAG.getRegister(StoreAddrReg, PtrVT));
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}
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SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
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