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Split scheduling from instruction selection.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-06-30 20:45:06 +00:00
parent 30389141c9
commit db8d56b825
11 changed files with 62 additions and 70 deletions
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12
include/llvm/CodeGen/SelectionDAGISel.h
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@ -58,7 +58,9 @@ public:
unsigned MakeReg(MVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
virtual void InstructionSelect(SelectionDAG &SD) = 0;
virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {}
virtual void SelectRootInit() {
DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
}
@ -160,10 +162,6 @@ public:
};
protected:
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
void ScheduleAndEmitDAG(SelectionDAG &DAG);
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
@ -187,6 +185,10 @@ private:
void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
void ScheduleAndEmitDAG(SelectionDAG &DAG);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.
std::vector<CaseBlock> SwitchCases;