mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-27 15:57:13 +00:00
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
30389141c9
commit
db8d56b825
@ -58,7 +58,9 @@ public:
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unsigned MakeReg(MVT VT);
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unsigned MakeReg(MVT VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
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virtual void InstructionSelect(SelectionDAG &SD) = 0;
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virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {}
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virtual void SelectRootInit() {
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virtual void SelectRootInit() {
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DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
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DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
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}
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}
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@ -160,10 +162,6 @@ public:
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};
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};
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protected:
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protected:
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &DAG);
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
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void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
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@ -187,6 +185,10 @@ private:
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void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
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void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &DAG);
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
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/// SwitchInst code generation information.
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std::vector<CaseBlock> SwitchCases;
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std::vector<CaseBlock> SwitchCases;
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@ -43,9 +43,10 @@
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Timer.h"
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#include <algorithm>
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#include <algorithm>
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using namespace llvm;
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using namespace llvm;
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@ -5354,7 +5355,14 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
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// Third, instruction select all of the operations to machine code, adding the
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// Third, instruction select all of the operations to machine code, adding the
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// code to the MachineBasicBlock.
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// code to the MachineBasicBlock.
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InstructionSelectBasicBlock(DAG);
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InstructionSelect(DAG);
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// Emit machine code to BB. This can change 'BB' to the last block being
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// inserted into.
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ScheduleAndEmitDAG(DAG);
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// Perform target specific isel post processing.
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InstructionSelectPostProcessing(DAG);
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DOUT << "Selected machine code:\n";
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DOUT << "Selected machine code:\n";
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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@ -54,7 +54,7 @@ public:
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}
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}
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SDNode *Select(SDOperand Op);
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SDNode *Select(SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
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bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &Opc);
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SDOperand &Offset, SDOperand &Opc);
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bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
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bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
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@ -91,13 +91,11 @@ public:
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};
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};
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}
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}
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void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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ScheduleAndEmitDAG(DAG);
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}
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}
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bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
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bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
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@ -161,9 +161,9 @@ namespace {
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// target-specific node if it hasn't already been changed.
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// target-specific node if it hasn't already been changed.
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SDNode *Select(SDOperand Op);
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SDNode *Select(SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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return "Alpha DAG->DAG Pattern Instruction Selection";
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@ -230,17 +230,14 @@ SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
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RA, MVT::i64);
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RA, MVT::i64);
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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}
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// Select - Convert the specified operand from a target-independent to a
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// Select - Convert the specified operand from a target-independent to a
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@ -317,9 +317,9 @@ public:
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return false;
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return false;
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "Cell SPU DAG->DAG Pattern Instruction Selection";
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return "Cell SPU DAG->DAG Pattern Instruction Selection";
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@ -339,19 +339,16 @@ public:
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void
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void
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SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
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SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG)
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{
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{
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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}
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/*!
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/*!
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@ -78,9 +78,9 @@ namespace {
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/// operation.
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/// operation.
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "IA64 (Itanium) DAG->DAG Instruction Selector";
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return "IA64 (Itanium) DAG->DAG Instruction Selector";
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@ -94,17 +94,14 @@ private:
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};
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};
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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}
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SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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@ -66,7 +66,7 @@ public:
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SelectionDAGISel(MipsLowering),
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SelectionDAGISel(MipsLowering),
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TM(tm), MipsLowering(*TM.getTargetLowering()) {}
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TM(tm), MipsLowering(*TM.getTargetLowering()) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
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virtual void InstructionSelect(SelectionDAG &SD);
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// Pass Name
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// Pass Name
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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@ -100,10 +100,10 @@ private:
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void MipsDAGToDAGISel::
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void MipsDAGToDAGISel::
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InstructionSelectBasicBlock(SelectionDAG &SD)
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InstructionSelect(SelectionDAG &SD)
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{
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{
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Codegen the basic block.
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// Codegen the basic block.
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@ -120,9 +120,6 @@ InstructionSelectBasicBlock(SelectionDAG &SD)
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#endif
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#endif
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SD.RemoveDeadNodes();
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SD.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(SD);
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}
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// getGlobalBaseReg - Output the instructions required to put the
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SelectionDAGISel(PIC16Lowering),
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SelectionDAGISel(PIC16Lowering),
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TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
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TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
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virtual void InstructionSelect(SelectionDAG &SD);
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// Pass Name
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// Pass Name
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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@ -97,9 +97,9 @@ private:
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD)
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void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD)
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{
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{
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Codegen the basic block.
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// Codegen the basic block.
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@ -115,9 +115,6 @@ void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD)
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DOUT << "===== Instruction selection ends:\n";
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DOUT << "===== Instruction selection ends:\n";
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SD.RemoveDeadNodes();
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SD.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(SD);
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}
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}
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@ -173,9 +173,9 @@ namespace {
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SDOperand BuildSDIVSequence(SDNode *N);
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SDOperand BuildSDIVSequence(SDNode *N);
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SDOperand BuildUDIVSequence(SDNode *N);
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SDOperand BuildUDIVSequence(SDNode *N);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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void InsertVRSaveCode(Function &Fn);
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void InsertVRSaveCode(Function &Fn);
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@ -201,17 +201,14 @@ private:
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};
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};
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}
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void PPCDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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}
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/// InsertVRSaveCode - Once the entire function has been instruction selected,
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/// InsertVRSaveCode - Once the entire function has been instruction selected,
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bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
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bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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SDOperand &Offset);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void InstructionSelect(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "SPARC DAG->DAG Pattern Instruction Selection";
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return "SPARC DAG->DAG Pattern Instruction Selection";
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@ -60,17 +60,14 @@ public:
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};
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};
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} // end anonymous namespace
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} // end anonymous namespace
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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}
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bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
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bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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||||||
#include "llvm/Support/Compiler.h"
|
#include "llvm/Support/Compiler.h"
|
||||||
#include "llvm/Support/Debug.h"
|
#include "llvm/Support/Debug.h"
|
||||||
#include "llvm/Support/MathExtras.h"
|
#include "llvm/Support/MathExtras.h"
|
||||||
@ -111,6 +110,10 @@ namespace {
|
|||||||
/// base register.
|
/// base register.
|
||||||
unsigned GlobalBaseReg;
|
unsigned GlobalBaseReg;
|
||||||
|
|
||||||
|
/// CurBB - Current BB being isel'd.
|
||||||
|
///
|
||||||
|
MachineBasicBlock *CurBB;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
|
X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
|
||||||
: SelectionDAGISel(X86Lowering),
|
: SelectionDAGISel(X86Lowering),
|
||||||
@ -128,9 +131,13 @@ namespace {
|
|||||||
return "X86 DAG->DAG Instruction Selection";
|
return "X86 DAG->DAG Instruction Selection";
|
||||||
}
|
}
|
||||||
|
|
||||||
/// InstructionSelectBasicBlock - This callback is invoked by
|
/// InstructionSelect - This callback is invoked by
|
||||||
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
||||||
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
|
virtual void InstructionSelect(SelectionDAG &DAG);
|
||||||
|
|
||||||
|
/// InstructionSelectPostProcessing - Post processing of selected and
|
||||||
|
/// scheduled basic blocks.
|
||||||
|
virtual void InstructionSelectPostProcessing(SelectionDAG &DAG);
|
||||||
|
|
||||||
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
|
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
|
||||||
|
|
||||||
@ -554,10 +561,10 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
|
|||||||
|
|
||||||
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
|
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
|
||||||
/// when it has created a SelectionDAG for us to codegen.
|
/// when it has created a SelectionDAG for us to codegen.
|
||||||
void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
|
||||||
DEBUG(BB->dump());
|
CurBB = BB; // BB can change as result of isel.
|
||||||
MachineFunction::iterator FirstMBB = BB;
|
|
||||||
|
|
||||||
|
DEBUG(BB->dump());
|
||||||
if (!FastISel)
|
if (!FastISel)
|
||||||
PreprocessForRMW(DAG);
|
PreprocessForRMW(DAG);
|
||||||
|
|
||||||
@ -575,11 +582,9 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
DAG.RemoveDeadNodes();
|
DAG.RemoveDeadNodes();
|
||||||
|
}
|
||||||
|
|
||||||
// Emit machine code to BB. This can change 'BB' to the last block being
|
void X86DAGToDAGISel::InstructionSelectPostProcessing(SelectionDAG &DAG) {
|
||||||
// inserted into.
|
|
||||||
ScheduleAndEmitDAG(DAG);
|
|
||||||
|
|
||||||
// If we are emitting FP stack code, scan the basic block to determine if this
|
// If we are emitting FP stack code, scan the basic block to determine if this
|
||||||
// block defines any FP values. If so, put an FP_REG_KILL instruction before
|
// block defines any FP values. If so, put an FP_REG_KILL instruction before
|
||||||
// the terminator of the block.
|
// the terminator of the block.
|
||||||
@ -592,7 +597,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
|||||||
|
|
||||||
// Scan all of the machine instructions in these MBBs, checking for FP
|
// Scan all of the machine instructions in these MBBs, checking for FP
|
||||||
// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
|
// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
|
||||||
MachineFunction::iterator MBBI = FirstMBB;
|
MachineFunction::iterator MBBI = CurBB;
|
||||||
MachineFunction::iterator EndMBB = BB; ++EndMBB;
|
MachineFunction::iterator EndMBB = BB; ++EndMBB;
|
||||||
for (; MBBI != EndMBB; ++MBBI) {
|
for (; MBBI != EndMBB; ++MBBI) {
|
||||||
MachineBasicBlock *MBB = MBBI;
|
MachineBasicBlock *MBB = MBBI;
|
||||||
|
Loading…
Reference in New Issue
Block a user