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Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and

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SRA_PARTS, as is done for SRL, SHL, and SRA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-08-18 23:36:17 +00:00
parent ab81027544
commit db8dc2b9fa
2 changed files with 29 additions and 0 deletions
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7
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -898,6 +898,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (!Ops[1].getValueType().isVector())
Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
break;
case ISD::SRL_PARTS:
case ISD::SRA_PARTS:
case ISD::SHL_PARTS:
// Legalizing shifts/rotates requires adjusting the shift amount
// to the appropriate width.
if (!Ops[2].getValueType().isVector())
Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
}
Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),

22
test/CodeGen/X86/shift-parts.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep shrdq
; PR4736
%0 = type { i32, i8, [35 x i8] }
@g_144 = external global %0, align 8 ; <%0*> [#uses=1]
define i32 @int87(i32 %uint64p_8) nounwind {
entry:
%srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
br label %for.cond
for.cond: ; preds = %for.cond, %entry
%call3.in.in.in.v = select i1 undef, i320 192, i320 128 ; <i320> [#uses=1]
%call3.in.in.in = lshr i320 %srcval4, %call3.in.in.in.v ; <i320> [#uses=1]
%call3.in = trunc i320 %call3.in.in.in to i32 ; <i32> [#uses=1]
%tobool = icmp eq i32 %call3.in, 0 ; <i1> [#uses=1]
br i1 %tobool, label %for.cond, label %if.then
if.then: ; preds = %for.cond
ret i32 1
}