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Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and
SRA_PARTS, as is done for SRL, SHL, and SRA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79380 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -898,6 +898,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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if (!Ops[1].getValueType().isVector())
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Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
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break;
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case ISD::SRL_PARTS:
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case ISD::SRA_PARTS:
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case ISD::SHL_PARTS:
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// Legalizing shifts/rotates requires adjusting the shift amount
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// to the appropriate width.
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if (!Ops[2].getValueType().isVector())
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Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
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}
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Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
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22
test/CodeGen/X86/shift-parts.ll
Normal file
22
test/CodeGen/X86/shift-parts.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llvm-as < %s | llc -march=x86-64 | grep shrdq
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; PR4736
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%0 = type { i32, i8, [35 x i8] }
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@g_144 = external global %0, align 8 ; <%0*> [#uses=1]
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define i32 @int87(i32 %uint64p_8) nounwind {
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entry:
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%srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
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br label %for.cond
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for.cond: ; preds = %for.cond, %entry
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%call3.in.in.in.v = select i1 undef, i320 192, i320 128 ; <i320> [#uses=1]
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%call3.in.in.in = lshr i320 %srcval4, %call3.in.in.in.v ; <i320> [#uses=1]
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%call3.in = trunc i320 %call3.in.in.in to i32 ; <i32> [#uses=1]
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%tobool = icmp eq i32 %call3.in, 0 ; <i1> [#uses=1]
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br i1 %tobool, label %for.cond, label %if.then
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if.then: ; preds = %for.cond
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ret i32 1
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}
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