6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Increase the number of floating point control registers available to 32.

Browse Source 
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-07-01 20:31:44 +00:00
parent ae99e41ff4
commit db8e0bbedb
5 changed files with 25 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -248,8 +248,9 @@ let Namespace = "Mips" in {
def LO64 : RegisterWithSubRegs<"lo", [LO]>;
}
// Status flags register
def FCR31 : Register<"31">;
// FP control registers.
foreach I = 0-31 in
def FCR#I : MipsReg<#I, ""#I>;
// fcc0 register
def FCC0 : MipsReg<0, "fcc0">;
@ -357,8 +358,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
// Condition Register for floating point operations
def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
// FP control registers.
def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
Unallocatable;
// FP condition code registers.
def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
// Hi/Lo Registers
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;

8
test/MC/Disassembler/Mips/mips32.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e
# CHECK: cfc1 $6, $fcc0
0x44 0x46 0x08 0x00
# CHECK: cfc1 $6, $7
0x44 0x46 0x38 0x00
# CHECK: clo $6, $7
0x70 0xe6 0x30 0x21
@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x70 0xe6 0x30 0x20
# CHECK: ctc1 $6, $fcc0
0x44 0xc6 0x08 0x00
# CHECK: ctc1 $6, $7
0x44 0xc6 0x38 0x00
# CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1

8
test/MC/Disassembler/Mips/mips32_le.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46
# CHECK: cfc1 $6, $fcc0
0x00 0x08 0x46 0x44
# CHECK: cfc1 $6, $7
0x00 0x38 0x46 0x44
# CHECK: clo $6, $7
0x21 0x30 0xe6 0x70
@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x20 0x30 0xe6 0x70
# CHECK: ctc1 $6, $fcc0
0x00 0x08 0xc6 0x44
# CHECK: ctc1 $6, $7
0x00 0x38 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46

8
test/MC/Disassembler/Mips/mips32r2.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e
# CHECK: cfc1 $6, $fcc0
0x44 0x46 0x08 0x00
# CHECK: cfc1 $6, $7
0x44 0x46 0x38 0x00
# CHECK: clo $6, $7
0x70 0xe6 0x30 0x21
@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x70 0xe6 0x30 0x20
# CHECK: ctc1 $6, $fcc0
0x44 0xc6 0x08 0x00
# CHECK: ctc1 $6, $7
0x44 0xc6 0x38 0x00
# CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1

8
test/MC/Disassembler/Mips/mips32r2_le.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46
# CHECK: cfc1 $6, $fcc0
0x00 0x08 0x46 0x44
# CHECK: cfc1 $6, $7
0x00 0x38 0x46 0x44
# CHECK: clo $6, $7
0x21 0x30 0xe6 0x70
@ -167,8 +167,8 @@
# CHECK: clz $6, $7
0x20 0x30 0xe6 0x70
# CHECK: ctc1 $6, $fcc0
0x00 0x08 0xc6 0x44
# CHECK: ctc1 $6, $7
0x00 0x38 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46