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Combine an unaligned store of unaligned load into a memmove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -153,6 +153,9 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
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maxStoresPerMemset = 4;
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maxStoresPerMemmove = maxStoresPerMemcpy = 2;
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine(ISD::STORE);
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}
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SDValue XCoreTargetLowering::
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@ -1049,6 +1052,55 @@ XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return BB;
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}
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//===----------------------------------------------------------------------===//
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// Target Optimization Hooks
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//===----------------------------------------------------------------------===//
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SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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DebugLoc dl = N->getDebugLoc();
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switch (N->getOpcode()) {
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default: break;
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case ISD::STORE: {
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// Replace unaligned store of unaligned load with memmove.
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StoreSDNode *ST = cast<StoreSDNode>(N);
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if (!DCI.isBeforeLegalize() || allowsUnalignedMemoryAccesses() ||
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ST->isVolatile() || ST->isIndexed()) {
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break;
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}
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SDValue Chain = ST->getChain();
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unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
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if (StoreBits % 8) {
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break;
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}
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unsigned ABIAlignment = getTargetData()->
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getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(*DAG.getContext()));
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unsigned Alignment = ST->getAlignment();
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if (Alignment >= ABIAlignment) {
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break;
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}
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
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if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
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LD->getAlignment() == Alignment &&
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!LD->isVolatile() && !LD->isIndexed() &&
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Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
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return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
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LD->getBasePtr(),
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DAG.getConstant(StoreBits/8, MVT::i32),
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Alignment, ST->getSrcValue(),
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ST->getSrcValueOffset(), LD->getSrcValue(),
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LD->getSrcValueOffset());
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}
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}
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break;
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}
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}
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return SDValue();
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}
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//===----------------------------------------------------------------------===//
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// Addressing mode description hooks
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//===----------------------------------------------------------------------===//
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@ -122,6 +122,8 @@ namespace llvm {
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// Expand specifics
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SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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};
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}
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12
test/CodeGen/XCore/unaligned_store_combine.ll
Normal file
12
test/CodeGen/XCore/unaligned_store_combine.ll
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@ -0,0 +1,12 @@
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; RUN: llvm-as < %s | llc -march=xcore > %t1.s
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; RUN: grep "bl memmove" %t1.s | count 1
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; RUN: grep "ldc r., 8" %t1.s | count 1
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; Unaligned load / store pair. Should be combined into a memmove
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; of size 8
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define void @f(i64* %dst, i64* %src) nounwind {
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entry:
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%0 = load i64* %src, align 1
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store i64 %0, i64* %dst, align 1
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ret void
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}
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