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Change the prototype for TargetLowering::isOperandValidForConstraint

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-10-31 19:40:43 +00:00
parent cbea67f55b
commit dba1aeedd8
4 changed files with 34 additions and 20 deletions
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9
include/llvm/Target/TargetLowering.h
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@ -694,9 +694,12 @@ public:
MVT::ValueType VT) const;
/// isOperandValidForConstraint - Return true if the specified SDOperand is
/// valid for the specified target constraint letter.
virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
/// isOperandValidForConstraint - Return the specified operand (possibly
/// modified) if the specified SDOperand is valid for the specified target
/// constraint letter, otherwise return null.
virtual SDOperand
isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
SelectionDAG &DAG);
//===--------------------------------------------------------------------===//
// Scheduler hooks

13
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1300,18 +1300,21 @@ TargetLowering::getConstraintType(char ConstraintLetter) const {
}
}
bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
char ConstraintLetter) {
/// isOperandValidForConstraint - Return the specified operand (possibly
/// modified) if the specified SDOperand is valid for the specified target
/// constraint letter, otherwise return null.
SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
char ConstraintLetter,
SelectionDAG &DAG) {
switch (ConstraintLetter) {
default: return false;
default: return SDOperand(0,0);
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
return true; // FIXME: not right.
return Op; // FIXME: not right.
}
}
std::vector<unsigned> TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {

29
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -2658,8 +2658,8 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
}
// isOperandValidForConstraint
bool PPCTargetLowering::
isOperandValidForConstraint(SDOperand Op, char Letter) {
SDOperand PPCTargetLowering::
isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
switch (Letter) {
default: break;
case 'I':
@ -2670,32 +2670,39 @@ isOperandValidForConstraint(SDOperand Op, char Letter) {
case 'N':
case 'O':
case 'P': {
if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
unsigned Value = cast<ConstantSDNode>(Op)->getValue();
switch (Letter) {
default: assert(0 && "Unknown constraint letter!");
case 'I': // "I" is a signed 16-bit constant.
return (short)Value == (int)Value;
if ((short)Value == (int)Value) return Op;
break;
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
return (short)Value == 0;
if ((short)Value == 0) return Op;
break;
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
return (Value >> 16) == 0;
if ((Value >> 16) == 0) return Op;
break;
case 'M': // "M" is a constant that is greater than 31.
return Value > 31;
if (Value > 31) return Op;
break;
case 'N': // "N" is a positive constant that is an exact power of two.
return (int)Value > 0 && isPowerOf2_32(Value);
if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
break;
case 'O': // "O" is the constant zero.
return Value == 0;
if (Value == 0) return Op;
break;
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
return (short)-Value == (int)-Value;
if ((short)-Value == (int)-Value) return Op;
break;
}
break;
}
}
// Handle standard constraint letters.
return TargetLowering::isOperandValidForConstraint(Op, Letter);
return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
}
/// isLegalAddressImmediate - Return true if the integer value can be used

3
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -194,7 +194,8 @@ namespace llvm {
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
SelectionDAG &DAG);
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.