From dbd3c0e06dcd4b94c291388b365a93a3710335af Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 12 Aug 2009 00:49:01 +0000 Subject: [PATCH] Add missing chain operands for VLD* and VST* instructions. Set "mayLoad" and "mayStore" on the load/store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelDAGToDAG.cpp | 30 ++++++++++++++++++------------ lib/Target/ARM/ARMInstrNEON.td | 30 ++++++++++++++++-------------- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index af1e57b3e6f..e8c1901b014 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1357,8 +1357,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD2d32; break; } - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3); + SDValue Chain = N->getOperand(0); + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; + return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4); } case ARMISD::VLD3D: { @@ -1374,8 +1375,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD3d32; break; } - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3); + SDValue Chain = N->getOperand(0); + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; + return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4); } case ARMISD::VLD4D: { @@ -1391,10 +1393,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD4d32; break; } - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; + SDValue Chain = N->getOperand(0); + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; std::vector ResTys(4, VT); ResTys.push_back(MVT::Other); - return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3); + return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4); } case ARMISD::VST2D: { @@ -1409,9 +1412,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VST2d32; break; } + SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, - N->getOperand(2), N->getOperand(3) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5); + N->getOperand(2), N->getOperand(3), Chain }; + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6); } case ARMISD::VST3D: { @@ -1426,10 +1430,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VST3d32; break; } + SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(2), N->getOperand(3), - N->getOperand(4) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6); + N->getOperand(4), Chain }; + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7); } case ARMISD::VST4D: { @@ -1444,10 +1449,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v2f32: case MVT::v2i32: Opc = ARM::VST4d32; break; } + SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(2), N->getOperand(3), - N->getOperand(4), N->getOperand(5) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7); + N->getOperand(4), N->getOperand(5), Chain }; + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8); } case ISD::INTRINSIC_WO_CHAIN: { diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 32baec5f073..d2ef593c101 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -113,8 +113,8 @@ def addrmode_neonldstm : Operand, // NEON load / store instructions //===----------------------------------------------------------------------===// -/* TODO: Take advantage of vldm. let mayLoad = 1 in { +/* TODO: Take advantage of vldm. def VLDMD : NI<(outs), (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), NoItinerary, @@ -134,7 +134,6 @@ def VLDMS : NI<(outs), let Inst{20} = 1; let Inst{11-9} = 0b101; } -} */ // Use vldmia to load a Q register as a D register pair. @@ -149,18 +148,6 @@ def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr), let Inst{11-9} = 0b101; } -// Use vstmia to store a Q register as a D register pair. -def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), - NoItinerary, - "vstmia $addr, ${src:dregpair}", - [(store (v2f64 QPR:$src), addrmode4:$addr)]> { - let Inst{27-25} = 0b110; - let Inst{24} = 0; // P bit - let Inst{23} = 1; // U bit - let Inst{20} = 0; - let Inst{11-9} = 0b101; -} - // VLD1 : Vector Load (multiple single elements) class VLD1D : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), @@ -215,6 +202,20 @@ class VLD4D def VLD4d8 : VLD4D<"vld4.8">; def VLD4d16 : VLD4D<"vld4.16">; def VLD4d32 : VLD4D<"vld4.32">; +} + +let mayStore = 1 in { +// Use vstmia to store a Q register as a D register pair. +def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), + NoItinerary, + "vstmia $addr, ${src:dregpair}", + [(store (v2f64 QPR:$src), addrmode4:$addr)]> { + let Inst{27-25} = 0b110; + let Inst{24} = 0; // P bit + let Inst{23} = 1; // U bit + let Inst{20} = 0; + let Inst{11-9} = 0b101; +} // VST1 : Vector Store (multiple single elements) class VST1D @@ -268,6 +269,7 @@ class VST4D def VST4d8 : VST4D<"vst4.8">; def VST4d16 : VST4D<"vst4.16">; def VST4d32 : VST4D<"vst4.32">; +} //===----------------------------------------------------------------------===//