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https://github.com/c64scene-ar/llvm-6502.git
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Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -63,19 +63,20 @@ namespace llvm {
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v1i64 = 24, // 1 x i64
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v2i64 = 25, // 2 x i64
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v4i64 = 26, // 4 x i64
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v8i64 = 27, // 8 x i64
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v2f32 = 27, // 2 x f32
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v4f32 = 28, // 4 x f32
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v8f32 = 29, // 8 x f32
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v2f64 = 30, // 2 x f64
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v4f64 = 31, // 4 x f64
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v2f32 = 28, // 2 x f32
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v4f32 = 29, // 4 x f32
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v8f32 = 30, // 8 x f32
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v2f64 = 31, // 2 x f64
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v4f64 = 32, // 4 x f64
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FIRST_VECTOR_VALUETYPE = v2i8,
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LAST_VECTOR_VALUETYPE = v4f64,
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Flag = 32, // This glues nodes together during pre-RA sched
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Flag = 33, // This glues nodes together during pre-RA sched
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isVoid = 33, // This has no value
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isVoid = 34, // This has no value
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LAST_VALUETYPE = 34, // This always remains at the end of the list.
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@@ -140,7 +141,7 @@ namespace llvm {
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bool isInteger() const {
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return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
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SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
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(SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v4i64));
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(SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64));
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}
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/// isVector - Return true if this is a vector value type.
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@@ -192,7 +193,8 @@ namespace llvm {
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case v8i32: return i32;
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case v1i64:
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case v2i64:
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case v4i64: return i64;
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case v4i64:
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case v8i64: return i64;
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case v2f32:
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case v4f32:
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case v8f32: return f32;
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@@ -211,6 +213,7 @@ namespace llvm {
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case v8i8 :
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case v8i16:
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case v8i32:
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case v8i64:
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case v8f32: return 8;
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case v4i8:
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case v4i16:
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@@ -269,6 +272,7 @@ namespace llvm {
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case v4i64:
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case v8f32:
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case v4f64: return 256;
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case v8i64: return 512;
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}
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}
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@@ -332,6 +336,7 @@ namespace llvm {
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if (NumElements == 1) return MVT::v1i64;
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if (NumElements == 2) return MVT::v2i64;
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if (NumElements == 4) return MVT::v4i64;
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if (NumElements == 8) return MVT::v8i64;
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break;
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case MVT::f32:
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if (NumElements == 2) return MVT::v2f32;
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@@ -468,10 +473,15 @@ namespace llvm {
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/// is256BitVector - Return true if this is a 256-bit vector type.
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inline bool is256BitVector() const {
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return isSimple() ?
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(V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 ||
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V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) :
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isExtended256BitVector();
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return isSimple()
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? (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 ||
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V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64)
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: isExtended256BitVector();
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}
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/// is512BitVector - Return true if this is a 512-bit vector type.
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inline bool is512BitVector() const {
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return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector();
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}
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/// isOverloaded - Return true if this is an overloaded type for TableGen.
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@@ -668,6 +678,7 @@ namespace llvm {
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bool isExtended64BitVector() const;
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bool isExtended128BitVector() const;
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bool isExtended256BitVector() const;
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bool isExtended512BitVector() const;
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EVT getExtendedVectorElementType() const;
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unsigned getExtendedVectorNumElements() const;
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unsigned getExtendedSizeInBits() const;
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