6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

[SystemZ] Add ARK, AGRK, SRK and SGRK

Browse Source 
The testsuite changes follow the same lines as for r186683.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-07-19 16:26:39 +00:00
parent 52b2774577
commit dc05e0bff6
14 changed files with 186 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -535,8 +535,8 @@ def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
def AR : BinaryRR <"a", 0x1A, add, GR32, GR32>;
def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>;
defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
}
def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
@ -599,9 +599,9 @@ let Defs = [CC], Uses = [CC] in {
// add-immediate instruction instead.
let Defs = [CC] in {
// Subtraction of a register.
def SR : BinaryRR <"s", 0x1B, sub, GR32, GR32>;
defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
def SGR : BinaryRRE<"sg", 0xB909, sub, GR64, GR64>;
defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
// Subtraction of memory.
defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;

2
test/CodeGen/SystemZ/atomicrmw-add-03.ll
View File

@ -1,6 +1,6 @@
; Test 32-bit atomic additions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {

2
test/CodeGen/SystemZ/atomicrmw-add-04.ll
View File

@ -1,6 +1,6 @@
; Test 64-bit atomic additions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {

2
test/CodeGen/SystemZ/atomicrmw-sub-03.ll
View File

@ -1,6 +1,6 @@
; Test 32-bit atomic subtractions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {

2
test/CodeGen/SystemZ/atomicrmw-sub-04.ll
View File

@ -1,6 +1,6 @@
; Test 64-bit atomic subtractions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {

3
test/CodeGen/SystemZ/int-add-02.ll
View File

@ -1,6 +1,7 @@
; Test 32-bit addition in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()

3
test/CodeGen/SystemZ/int-add-05.ll
View File

@ -1,6 +1,7 @@
; Test 64-bit addition in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()

39
test/CodeGen/SystemZ/int-add-13.ll Normal file
View File

@ -0,0 +1,39 @@
; Test the three-operand forms of addition.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
; Check ARK.
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1:
; CHECK: ark %r2, %r3, %r4
; CHECK: br %r14
%add = add i32 %b, %c
ret i32 %add
}
; Check that we can still use AR in obvious cases.
define i32 @f2(i32 %a, i32 %b) {
; CHECK-LABEL: f2:
; CHECK: ar %r2, %r3
; CHECK: br %r14
%add = add i32 %a, %b
ret i32 %add
}
; Check AGRK.
define i64 @f3(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f3:
; CHECK: agrk %r2, %r3, %r4
; CHECK: br %r14
%add = add i64 %b, %c
ret i64 %add
}
; Check that we can still use AGR in obvious cases.
define i64 @f4(i64 %a, i64 %b) {
; CHECK-LABEL: f4:
; CHECK: agr %r2, %r3
; CHECK: br %r14
%add = add i64 %a, %b
ret i64 %add
}

3
test/CodeGen/SystemZ/int-sub-01.ll
View File

@ -1,6 +1,7 @@
; Test 32-bit subtraction.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()

3
test/CodeGen/SystemZ/int-sub-04.ll
View File

@ -1,6 +1,7 @@
; Test 64-bit subtraction in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()

39
test/CodeGen/SystemZ/int-sub-08.ll Normal file
View File

@ -0,0 +1,39 @@
; Test the three-operand forms of subtraction.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
; Check SRK.
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1:
; CHECK: srk %r2, %r3, %r4
; CHECK: br %r14
%sub = sub i32 %b, %c
ret i32 %sub
}
; Check that we can still use SR in obvious cases.
define i32 @f2(i32 %a, i32 %b) {
; CHECK-LABEL: f2:
; CHECK: sr %r2, %r3
; CHECK: br %r14
%sub = sub i32 %a, %b
ret i32 %sub
}
; Check SGRK.
define i64 @f3(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: f3:
; CHECK: sgrk %r2, %r3, %r4
; CHECK: br %r14
%sub = sub i64 %b, %c
ret i64 %sub
}
; Check that we can still use SGR in obvious cases.
define i64 @f4(i64 %a, i64 %b) {
; CHECK-LABEL: f4:
; CHECK: sgr %r2, %r3
; CHECK: br %r14
%sub = sub i64 %a, %b
ret i64 %sub
}

24
test/MC/Disassembler/SystemZ/insns.txt
View File

@ -175,6 +175,12 @@
# CHECK: agr %r7, %r8
0xb9 0x08 0x00 0x78
# CHECK: agrk %r0, %r0, %r0
0xb9 0xe8 0x00 0x00
# CHECK: agrk %r2, %r3, %r4
0xb9 0xe8 0x40 0x23
# CHECK: agsi -524288, 0
0xeb 0x00 0x00 0x00 0x80 0x7a
@ -574,6 +580,12 @@
# CHECK: ar %r7, %r8
0x1a 0x78
# CHECK: ark %r0, %r0, %r0
0xb9 0xf8 0x00 0x00
# CHECK: ark %r2, %r3, %r4
0xb9 0xf8 0x40 0x23
# CHECK: asi -524288, 0
0xeb 0x00 0x00 0x00 0x80 0x6a
@ -4936,6 +4948,12 @@
# CHECK: sgr %r7, %r8
0xb9 0x09 0x00 0x78
# CHECK: sgrk %r0, %r0, %r0
0xb9 0xe9 0x00 0x00
# CHECK: sgrk %r2, %r3, %r4
0xb9 0xe9 0x40 0x23
# CHECK: sg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x09
@ -5644,6 +5662,12 @@
# CHECK: sr %r7, %r8
0x1b 0x78
# CHECK: srk %r0, %r0, %r0
0xb9 0xf9 0x00 0x00
# CHECK: srk %r2, %r3, %r4
0xb9 0xf9 0x40 0x23
# CHECK: stc %r0, 0
0x42 0x00 0x00 0x00

20
test/MC/SystemZ/insn-bad.s
View File

@ -69,6 +69,11 @@
aghi %r0, 32768
aghi %r0, foo
#CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: agrk %r2,%r3,%r4
agrk %r2,%r3,%r4
#CHECK: error: invalid operand
#CHECK: agsi -524289, 0
#CHECK: error: invalid operand
@ -177,6 +182,11 @@
aly %r0, -524289
aly %r0, 524288
#CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: ark %r2,%r3,%r4
ark %r2,%r3,%r4
#CHECK: error: invalid operand
#CHECK: asi -524289, 0
#CHECK: error: invalid operand
@ -2264,6 +2274,11 @@
sgf %r0, -524289
sgf %r0, 524288
#CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: sgrk %r2,%r3,%r4
sgrk %r2,%r3,%r4
#CHECK: error: invalid operand
#CHECK: sh %r0, -1
#CHECK: error: invalid operand
@ -2434,6 +2449,11 @@
srak %r2,%r3,4(%r5)
#CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: srk %r2,%r3,%r4
srk %r2,%r3,%r4
#CHECK: error: invalid operand
#CHECK: srl %r0,-1
#CHECK: error: invalid operand

48
test/MC/SystemZ/insn-good-z196.s
View File

@ -1,6 +1,30 @@
# For z196 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
#CHECK: agrk %r0, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0x00]
#CHECK: agrk %r0, %r0, %r15 # encoding: [0xb9,0xe8,0xf0,0x00]
#CHECK: agrk %r0, %r15, %r0 # encoding: [0xb9,0xe8,0x00,0x0f]
#CHECK: agrk %r15, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0xf0]
#CHECK: agrk %r7, %r8, %r9 # encoding: [0xb9,0xe8,0x90,0x78]
agrk %r0,%r0,%r0
agrk %r0,%r0,%r15
agrk %r0,%r15,%r0
agrk %r15,%r0,%r0
agrk %r7,%r8,%r9
#CHECK: ark %r0, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0x00]
#CHECK: ark %r0, %r0, %r15 # encoding: [0xb9,0xf8,0xf0,0x00]
#CHECK: ark %r0, %r15, %r0 # encoding: [0xb9,0xf8,0x00,0x0f]
#CHECK: ark %r15, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0xf0]
#CHECK: ark %r7, %r8, %r9 # encoding: [0xb9,0xf8,0x90,0x78]
ark %r0,%r0,%r0
ark %r0,%r0,%r15
ark %r0,%r15,%r0
ark %r15,%r0,%r0
ark %r7,%r8,%r9
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
@ -49,6 +73,18 @@
ork %r15,%r0,%r0
ork %r7,%r8,%r9
#CHECK: sgrk %r0, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0x00]
#CHECK: sgrk %r0, %r0, %r15 # encoding: [0xb9,0xe9,0xf0,0x00]
#CHECK: sgrk %r0, %r15, %r0 # encoding: [0xb9,0xe9,0x00,0x0f]
#CHECK: sgrk %r15, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0xf0]
#CHECK: sgrk %r7, %r8, %r9 # encoding: [0xb9,0xe9,0x90,0x78]
sgrk %r0,%r0,%r0
sgrk %r0,%r0,%r15
sgrk %r0,%r15,%r0
sgrk %r15,%r0,%r0
sgrk %r7,%r8,%r9
#CHECK: sllk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
@ -101,6 +137,18 @@
srak %r0,%r0,524287(%r1)
srak %r0,%r0,524287(%r15)
#CHECK: srk %r0, %r0, %r0 # encoding: [0xb9,0xf9,0x00,0x00]
#CHECK: srk %r0, %r0, %r15 # encoding: [0xb9,0xf9,0xf0,0x00]
#CHECK: srk %r0, %r15, %r0 # encoding: [0xb9,0xf9,0x00,0x0f]
#CHECK: srk %r15, %r0, %r0 # encoding: [0xb9,0xf9,0x00,0xf0]
#CHECK: srk %r7, %r8, %r9 # encoding: [0xb9,0xf9,0x90,0x78]
srk %r0,%r0,%r0
srk %r0,%r0,%r15
srk %r0,%r15,%r0
srk %r15,%r0,%r0
srk %r7,%r8,%r9
#CHECK: srlk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xde]
#CHECK: srlk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xde]
#CHECK: srlk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xde]