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Add patterns for various extloads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
3360da9772
commit
dc28955b3f
@ -221,6 +221,9 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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if (Depth > 5)
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return MatchAddressBase(N, AM);
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// FIXME: We can perform better here. If we have something like
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// (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
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// imm into addressing mode.
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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@ -108,6 +108,20 @@ def i64hi32 : PatLeaf<(i64 imm), [{
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return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
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}], HI32>;
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// extloads
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// SystemZ Operand Definitions.
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//===----------------------------------------------------------------------===//
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@ -200,10 +214,31 @@ def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgr\t{$dst, $src}",
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"lg\t{$dst, $src}",
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[(set GR64:$dst, (load rriaddr:$src))]>;
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}
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def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgb\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
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def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgh\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
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def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgf\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
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def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"llgc\t{$dst, $src}",
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[(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
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def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"llgh\t{$dst, $src}",
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[(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
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def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"llgf\t{$dst, $src}",
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[(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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@ -410,3 +445,8 @@ def : Pat<(i32 (trunc GR64:$src)),
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// sext_inreg patterns
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def : Pat<(sext_inreg GR64:$src, i32),
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(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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// extload patterns
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def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
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def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
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75
test/CodeGen/SystemZ/05-MemRegLoads.ll
Normal file
75
test/CodeGen/SystemZ/05-MemRegLoads.ll
Normal file
@ -0,0 +1,75 @@
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; RUN: llvm-as < %s | llc -march=systemz | not grep aghi
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; RUN: llvm-as < %s | llc -march=systemz | grep llgf | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llgh | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llgc | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep lgf | count 2
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; RUN: llvm-as < %s | llc -march=systemz | grep lgh | count 2
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; RUN: llvm-as < %s | llc -march=systemz | grep lgb | count 1
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target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
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target triple = "s390x-unknown-linux-gnu"
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define zeroext i64 @foo1(i64* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
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%tmp3 = load i64* %add.ptr2 ; <i64> [#uses=1]
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ret i64 %tmp3
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}
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define zeroext i32 @foo2(i32* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
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%tmp3 = load i32* %add.ptr2 ; <i32> [#uses=1]
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ret i32 %tmp3
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}
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define zeroext i16 @foo3(i16* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
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%tmp3 = load i16* %add.ptr2 ; <i16> [#uses=1]
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ret i16 %tmp3
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}
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define zeroext i8 @foo4(i8* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
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%tmp3 = load i8* %add.ptr2 ; <i8> [#uses=1]
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ret i8 %tmp3
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}
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define signext i64 @foo5(i64* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
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%tmp3 = load i64* %add.ptr2 ; <i64> [#uses=1]
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ret i64 %tmp3
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}
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define signext i32 @foo6(i32* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
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%tmp3 = load i32* %add.ptr2 ; <i32> [#uses=1]
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ret i32 %tmp3
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}
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define signext i16 @foo7(i16* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
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%tmp3 = load i16* %add.ptr2 ; <i16> [#uses=1]
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ret i16 %tmp3
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}
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define signext i8 @foo8(i8* nocapture %a, i64 %idx) nounwind readonly {
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entry:
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%add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
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%add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
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%tmp3 = load i8* %add.ptr2 ; <i8> [#uses=1]
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ret i8 %tmp3
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}
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