6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Add a deterministic finite automaton based packetizer for VLIW architectures

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anshuman Dasgupta
2011-12-01 21:10:21 +00:00
parent 18c7ec1344
commit dc81e5da27
7 changed files with 756 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
utils/TableGen/TableGen.cpp
View File

@@ -16,6 +16,7 @@
#include "CallingConvEmitter.h"
#include "CodeEmitterGen.h"
#include "DAGISelEmitter.h"
#include "DFAPacketizerEmitter.h"
#include "DisassemblerEmitter.h"
#include "EDEmitter.h"
#include "FastISelEmitter.h"
@@ -47,6 +48,7 @@ enum ActionType {
GenPseudoLowering,
GenCallingConv,
GenDAGISel,
GenDFAPacketizer,
GenFastISel,
GenSubtarget,
GenIntrinsic,
@@ -79,6 +81,8 @@ namespace {
"Generate assembly instruction matcher"),
clEnumValN(GenDAGISel, "gen-dag-isel",
"Generate a DAG instruction selector"),
clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
"Generate DFA Packetizer for VLIW targets"),
clEnumValN(GenFastISel, "gen-fast-isel",
"Generate a \"fast\" instruction selector"),
clEnumValN(GenSubtarget, "gen-subtarget",
@@ -134,6 +138,9 @@ public:
case GenDAGISel:
DAGISelEmitter(Records).run(OS);
break;
case GenDFAPacketizer:
DFAGen(Records).run(OS);
break;
case GenFastISel:
FastISelEmitter(Records).run(OS);
break;