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Implement TargetLowering::getPackedTypeBreakdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27270 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14,6 +14,7 @@
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/MathExtras.h"
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@ -141,6 +142,46 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return NULL;
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}
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/// getPackedTypeBreakdown - Packed types are broken down into some number of
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/// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
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/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
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///
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/// This method returns the number and type of the resultant breakdown.
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///
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MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
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unsigned &NumVals) const {
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// Figure out the right, legal destination reg to copy into.
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unsigned NumElts = PTy->getNumElements();
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MVT::ValueType EltTy = getValueType(PTy->getElementType());
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unsigned NumVectorRegs = 1;
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
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NumElts >>= 1;
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NumVectorRegs <<= 1;
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}
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MVT::ValueType VT;
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if (NumElts == 1)
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VT = EltTy;
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else
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VT = getVectorType(EltTy, NumElts);
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MVT::ValueType DestVT = getTypeToTransformTo(VT);
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if (DestVT < VT) {
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// Value is expanded, e.g. i64 -> i16.
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NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
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} else {
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// Otherwise, promotion or legal types use the same number of registers as
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// the vector decimated to the appropriate level.
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NumVals = NumVectorRegs;
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}
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return DestVT;
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}
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//===----------------------------------------------------------------------===//
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// Optimization Methods
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//===----------------------------------------------------------------------===//
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