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Optimization for SIGN_EXTEND operation on AVX.
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1221,6 +1221,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::LOAD);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::TRUNCATE);
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setTargetDAGCombine(ISD::SINT_TO_FP);
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if (Subtarget->is64Bit())
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@ -14641,6 +14642,55 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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if (!DCI.isBeforeLegalizeOps())
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return SDValue();
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if (!Subtarget->hasAVX()) return SDValue();
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// Optimize vectors in AVX mode
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// Sign extend v8i16 to v8i32 and
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// v4i32 to v4i64
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//
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// Divide input vector into two parts
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// for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
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// use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
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// concat the vectors to original VT
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EVT VT = N->getValueType(0);
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SDValue Op = N->getOperand(0);
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EVT OpVT = Op.getValueType();
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DebugLoc dl = N->getDebugLoc();
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if (((VT == MVT::v4i64) && (OpVT == MVT::v4i32)) ||
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((VT == MVT::v8i32) && (OpVT == MVT::v8i16))) {
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unsigned NumElems = OpVT.getVectorNumElements();
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SmallVector<int,8> ShufMask1(NumElems, -1);
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for (unsigned i=0; i< NumElems/2; i++) ShufMask1[i] = i;
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SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
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ShufMask1.data());
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SmallVector<int,8> ShufMask2(NumElems, -1);
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for (unsigned i=0; i< NumElems/2; i++) ShufMask2[i] = i+NumElems/2;
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SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
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ShufMask2.data());
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EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
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VT.getVectorNumElements()/2);
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OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
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OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
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}
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return SDValue();
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}
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static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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// (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
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@ -14886,6 +14936,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
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case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
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case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
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case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
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case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
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case X86ISD::SHUFP: // Handle all target specific shuffles
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@ -219,6 +219,9 @@ namespace llvm {
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VZEXT_MOVL - Vector move low and sign extend.
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VSEXT_MOVL,
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// VSHL, VSRL - 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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@ -71,6 +71,9 @@ def X86insrtps : SDNode<"X86ISD::INSERTPS",
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SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
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@ -5478,6 +5478,16 @@ let Predicates = [HasSSE41] in {
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(PMOVZXDQrm addr:$src)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
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def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
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}
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let Predicates = [HasSSE41] in {
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def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
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def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
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}
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multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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17
test/CodeGen/X86/avx-sext.ll
Executable file
17
test/CodeGen/X86/avx-sext.ll
Executable file
@ -0,0 +1,17 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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;CHECK: sext_8i16_to_8i32
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;CHECK: vpmovsxwd
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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;CHECK: sext_4i32_to_4i64
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;CHECK: vpmovsxdq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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