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Capture information about whether the target instructions have delay slots

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16550 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-09-28 18:33:50 +00:00
parent 18d19ca6df
commit dcc4a6f705
1 changed files with 9 additions and 0 deletions
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9
include/llvm/Target/TargetInstrInfo.h
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@ -48,6 +48,7 @@ const unsigned M_BRANCH_FLAG = 1 << 1;
const unsigned M_CALL_FLAG = 1 << 2;
const unsigned M_RET_FLAG = 1 << 3;
const unsigned M_BARRIER_FLAG = 1 << 4;
const unsigned M_DELAY_SLOT = 1 << 5;
const unsigned M_CC_FLAG = 1 << 6;
const unsigned M_LOAD_FLAG = 1 << 10;
const unsigned M_STORE_FLAG = 1 << 12;
@ -193,6 +194,7 @@ public:
bool isBarrier(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_BARRIER_FLAG;
}
bool isCall(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_CALL_FLAG;
}
@ -202,6 +204,13 @@ public:
bool isStore(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_STORE_FLAG;
}
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot(unsigned Opcode) const {
return get(Opcode).Flags & M_DELAY_SLOT;
}
virtual bool hasResultInterlock(MachineOpCode Opcode) const {
return true;
}