From dcc50a4aeee13e5bb7aec9f6a2e5ca80ef54c40d Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 18 May 2007 01:53:54 +0000
Subject: [PATCH] Mark calls non-predicable for now. Need to ensure it's the
 last instruction in the if-converted block or make sure it preserve condition
 code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrInfo.td | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 9616a07a1d9..7d941459be0 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -575,17 +575,17 @@ let isLoad = 1, isReturn = 1, isTerminator = 1 in
 let isCall = 1, noResults = 1, 
   Defs = [R0, R1, R2, R3, R12, LR,
           D0, D1, D2, D3, D4, D5, D6, D7] in {
-  def BL  : AXI<(ops i32imm:$func, pred:$p, variable_ops),
-                "bl$p ${func:call}",
+  def BL  : AXI<(ops i32imm:$func, variable_ops),
+                "bl ${func:call}",
                 [(ARMcall tglobaladdr:$func)]>;
   // ARMv5T and above
-  def BLX : AXI<(ops GPR:$dst, pred:$p, variable_ops),
-                "blx$p $dst",
+  def BLX : AXI<(ops GPR:$dst, variable_ops),
+                "blx $dst",
                 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AXIx2<(ops GPR:$dst, pred:$p, variable_ops),
-                  "mov$p lr, pc\n\tbx$p $dst",
+    def BX : AXIx2<(ops GPR:$dst, variable_ops),
+                  "mov lr, pc\n\tbx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
   }
 }
@@ -1110,8 +1110,8 @@ def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
 // __aeabi_read_tp preserves the registers r1-r3.
 let isCall = 1,
   Defs = [R0, R12, LR] in {
-  def TPsoft : AI<(ops),
-               "bl", " __aeabi_read_tp",
+  def TPsoft : AXI<(ops),
+               "bl __aeabi_read_tp",
                [(set R0, ARMthread_pointer)]>;
 }