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ARM64: enable more regression tests from AArch64

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-14 12:50:58 +00:00
parent 3c68c5c55e
commit dce294e7b1
12 changed files with 105 additions and 63 deletions
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108
test/CodeGen/AArch64/alloca.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc -mtriple=arm64 -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP %s
declare void @use_addr(i8*)
@ -8,23 +9,22 @@ define void @test_simple_alloca(i64 %n) {
%buf = alloca i8, i64 %n
; Make sure we align the stack change to 16 bytes:
; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15
; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0
; CHECK: {{mov|add}} x29
; CHECK: mov [[TMP:x[0-9]+]], sp
; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
; Make sure we change SP. It would be surprising if anything but x0 were used
; for the final sp, but it could be if it was then moved into x0.
; CHECK-DAG: mov [[TMP:x[0-9]+]], sp
; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]]
; CHECK: mov sp, x0
; CHECK: sub [[NEWSP:x[0-9]+]], [[TMP]], [[SPDELTA]]
; CHECK: mov sp, [[NEWSP]]
call void @use_addr(i8* %buf)
; CHECK: bl use_addr
ret void
; Make sure epilogue restores sp from fp
; CHECK: sub sp, x29, #16
; CHECK: ldp x29, x30, [sp, #16]
; CHECK: add sp, sp, #32
; CHECK: {{sub|mov}} sp, x29
; CHECK: ret
}
@ -32,51 +32,49 @@ declare void @use_addr_loc(i8*, i64*)
define i64 @test_alloca_with_local(i64 %n) {
; CHECK-LABEL: test_alloca_with_local:
; CHECK: sub sp, sp, #32
; CHECK: stp x29, x30, [sp, #16]
; CHECK-DAG: sub sp, sp, [[LOCAL_STACK:#[0-9]+]]
; CHECK-DAG: {{mov|add}} x29, sp
%loc = alloca i64
%buf = alloca i8, i64 %n
; Make sure we align the stack change to 16 bytes:
; CHECK-DAG: add [[SPDELTA:x[0-9]+]], x0, #15
; CHECK-DAG: and x0, [[SPDELTA]], #0xfffffffffffffff0
; CHECK: mov [[TMP:x[0-9]+]], sp
; CHECK: add [[SPDELTA_TMP:x[0-9]+]], x0, #15
; CHECK: and [[SPDELTA:x[0-9]+]], [[SPDELTA_TMP]], #0xfffffffffffffff0
; Make sure we change SP. It would be surprising if anything but x0 were used
; for the final sp, but it could be if it was then moved into x0.
; CHECK-DAG: mov [[TMP:x[0-9]+]], sp
; CHECK-DAG: sub x0, [[TMP]], [[SPDELTA]]
; CHECK: mov sp, x0
; CHECK: sub [[NEWSP:x[0-9]+]], [[TMP]], [[SPDELTA]]
; CHECK: mov sp, [[NEWSP]]
; Obviously suboptimal code here, but it to get &local in x1
; CHECK: sub [[TMP:x[0-9]+]], x29, [[LOC_FROM_FP:#[0-9]+]]
; CHECK: add x1, [[TMP]], #0
; CHECK: sub {{x[0-9]+}}, x29, #[[LOC_FROM_FP:[0-9]+]]
call void @use_addr_loc(i8* %buf, i64* %loc)
; CHECK: bl use_addr
%val = load i64* %loc
; CHECK: sub x[[TMP:[0-9]+]], x29, [[LOC_FROM_FP]]
; CHECK: ldr x0, [x[[TMP]]]
; CHECK-AARCH64: sub x[[TMP:[0-9]+]], x29, #[[LOC_FROM_FP]]
; CHECK-AARCH64: ldr x0, [x[[TMP]]]
; CHECK-ARM64: ldur x0, [x29, #-[[LOC_FROM_FP]]]
ret i64 %val
; Make sure epilogue restores sp from fp
; CHECK: sub sp, x29, #16
; CHECK: ldp x29, x30, [sp, #16]
; CHECK: add sp, sp, #32
; CHECK: {{sub|mov}} sp, x29
; CHECK: ret
}
define void @test_variadic_alloca(i64 %n, ...) {
; CHECK: test_variadic_alloca:
; CHECK-LABEL: test_variadic_alloca:
; CHECK: sub sp, sp, #208
; CHECK: stp x29, x30, [sp, #192]
; CHECK: add x29, sp, #192
; CHECK: sub [[TMP:x[0-9]+]], x29, #192
; CHECK: add x8, [[TMP]], #0
; CHECK-FP: str q7, [x8, #112]
; CHECK-AARCH64: sub sp, sp, #{{[0-9]+}}
; CHECK-AARCH64: add x29, sp, #192
; CHECK-AARCH64: sub [[TMP:x[0-9]+]], x29, #192
; CHECK-AARCH64: add x8, [[TMP]], #0
; CHECK-AARCH64-FP: str q7, [x8, #112]
; [...]
; CHECK-FP: str q1, [x8, #16]
; CHECK-AARCH64-FP: str q1, [x8, #16]
; CHECK-NOFP: sub sp, sp, #80
; CHECK-NOFP: stp x29, x30, [sp, #64]
@ -84,15 +82,28 @@ define void @test_variadic_alloca(i64 %n, ...) {
; CHECK-NOFP: sub [[TMP:x[0-9]+]], x29, #64
; CHECK-NOFP: add x8, [[TMP]], #0
; CHECK-ARM64: stp x29, x30, [sp, #-16]!
; CHECK-ARM64: mov x29, sp
; CHECK-ARM64: sub sp, sp, #192
; CHECK-ARM64: stp q6, q7, [x29, #-96]
; [...]
; CHECK-ARM64: stp q0, q1, [x29, #-192]
; CHECK-ARM64: stp x6, x7, [x29, #-16]
; [...]
; CHECK-ARM64: stp x2, x3, [x29, #-48]
%addr = alloca i8, i64 %n
call void @use_addr(i8* %addr)
; CHECK: bl use_addr
ret void
; CHECK: sub sp, x29, #192
; CHECK: ldp x29, x30, [sp, #192]
; CHECK: add sp, sp, #208
; CHECK-AARCH64: sub sp, x29, #192
; CHECK-AARCH64: ldp x29, x30, [sp, #192]
; CHECK-AARCH64: add sp, sp, #208
; CHECK-NOFP: sub sp, x29, #64
; CHECK-NOFP: ldp x29, x30, [sp, #64]
@ -102,11 +113,17 @@ define void @test_variadic_alloca(i64 %n, ...) {
define void @test_alloca_large_frame(i64 %n) {
; CHECK-LABEL: test_alloca_large_frame:
; CHECK: sub sp, sp, #496
; CHECK: stp x29, x30, [sp, #480]
; CHECK: add x29, sp, #480
; CHECK: sub sp, sp, #48
; CHECK: sub sp, sp, #1953, lsl #12
; CHECK-AARCH64: sub sp, sp, #496
; CHECK-AARCH64: stp x29, x30, [sp, #480]
; CHECK-AARCH64: add x29, sp, #480
; CHECK-AARCH64: sub sp, sp, #48
; CHECK-AARCH64: sub sp, sp, #1953, lsl #12
; CHECK-ARM64: stp x20, x19, [sp, #-32]!
; CHECK-ARM64: stp x29, x30, [sp, #16]
; CHECK-ARM64: add x29, sp, #16
; CHECK-ARM64: sub sp, sp, #7999488
; CHECK-ARM64: sub sp, sp, #512
%addr1 = alloca i8, i64 %n
%addr2 = alloca i64, i64 1000000
@ -114,9 +131,13 @@ define void @test_alloca_large_frame(i64 %n) {
call void @use_addr_loc(i8* %addr1, i64* %addr2)
ret void
; CHECK: sub sp, x29, #480
; CHECK: ldp x29, x30, [sp, #480]
; CHECK: add sp, sp, #496
; CHECK-AARCH64: sub sp, x29, #480
; CHECK-AARCH64: ldp x29, x30, [sp, #480]
; CHECK-AARCH64: add sp, sp, #496
; CHECK-ARM64: sub sp, x29, #16
; CHECK-ARM64: ldp x29, x30, [sp, #16]
; CHECK-ARM64: ldp x20, x19, [sp], #32
}
declare i8* @llvm.stacksave()
@ -124,7 +145,6 @@ declare void @llvm.stackrestore(i8*)
define void @test_scoped_alloca(i64 %n) {
; CHECK-LABEL: test_scoped_alloca:
; CHECK: sub sp, sp, #32
%sp = call i8* @llvm.stacksave()
; CHECK: mov [[SAVED_SP:x[0-9]+]], sp

5
test/CodeGen/AArch64/analyze-branch.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu < %s | FileCheck %s
; This test checks that LLVM can do basic stripping and reapplying of branches
; to basic blocks.
@ -168,7 +169,7 @@ define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
%tst = icmp eq i64 %bit, 0
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbz {{x[0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: bl test_false
@ -213,7 +214,7 @@ define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
%tst = icmp ne i64 %bit, 0
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbnz {{x[0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: bl test_false

1
test/CodeGen/AArch64/assertion-rc-mismatch.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=arm64 | FileCheck %s
; Test case related to <rdar://problem/15633429>.
; CHECK-LABEL: small

1
test/CodeGen/AArch64/atomic-ops-not-barriers.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
define i32 @foo(i32* %var, i1 %cond) {
; CHECK-LABEL: foo:

11
test/CodeGen/AArch64/basic-pic.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic %s -o - | FileCheck %s
; RUN: llc -mtriple=arm64 -verify-machineinstrs -relocation-model=pic %s -o - | FileCheck %s
@var = global i32 0
@ -7,7 +8,7 @@ define i32 @get_globalvar() {
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], #:got_lo12:var]
; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], {{#?}}:got_lo12:var]
; CHECK: ldr w0, [x[[GOTLOC]]]
ret i32 %val
@ -18,7 +19,7 @@ define i32* @get_globalvaraddr() {
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
; CHECK: ldr x0, [x[[GOTHI]], #:got_lo12:var]
; CHECK: ldr x0, [x[[GOTHI]], {{#?}}:got_lo12:var]
ret i32* @var
}
@ -30,7 +31,7 @@ define i32 @get_hiddenvar() {
%val = load i32* @hiddenvar
; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
; CHECK: ldr w0, [x[[HI]], #:lo12:hiddenvar]
; CHECK: ldr w0, [x[[HI]], {{#?}}:lo12:hiddenvar]
ret i32 %val
}
@ -40,7 +41,7 @@ define i32* @get_hiddenvaraddr() {
%val = load i32* @hiddenvar
; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
; CHECK: add x0, [[HI]], #:lo12:hiddenvar
; CHECK: add x0, [[HI]], {{#?}}:lo12:hiddenvar
ret i32* @hiddenvar
}
@ -50,5 +51,5 @@ define void()* @get_func() {
ret void()* bitcast(void()*()* @get_func to void()*)
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
; CHECK: ldr x0, [x[[GOTHI]], #:got_lo12:get_func]
; CHECK: ldr x0, [x[[GOTHI]], {{#?}}:got_lo12:get_func]
}

1
test/CodeGen/AArch64/bitfield-insert-0.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -disassemble - | FileCheck %s
; RUN: llc -mtriple=arm64 -filetype=obj -o - %s | llvm-objdump -disassemble - | FileCheck %s
; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
; point, in the edge case where lsb = 0. Just make sure.

4
test/CodeGen/AArch64/blockaddress.ll
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@ -1,5 +1,7 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -code-model=large -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s
@addr = global i8* null
@ -9,7 +11,7 @@ define void @test_blockaddress() {
%val = load volatile i8** @addr
indirectbr i8* %val, [label %block]
; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]]
; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], #:lo12:[[DEST_LBL]]
; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
; CHECK: str [[DEST]],
; CHECK: ldr [[NEWDEST:x[0-9]+]]
; CHECK: br [[NEWDEST]]

21
test/CodeGen/AArch64/bool-loads.ll
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@ -1,54 +1,55 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=arm64 -o - %s | FileCheck %s
@var = global i1 0
define i32 @test_sextloadi32() {
; CHECK: test_sextloadi32
; CHECK-LABEL: test_sextloadi32
%val = load i1* @var
%ret = sext i1 %val to i32
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm w[0-9]+, w[0-9]+, #0, #0}}
ret i32 %ret
; CHECK: ret
}
define i64 @test_sextloadi64() {
; CHECK: test_sextloadi64
; CHECK-LABEL: test_sextloadi64
%val = load i1* @var
%ret = sext i1 %val to i64
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #1
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm x[0-9]+, x[0-9]+, #0, #0}}
ret i64 %ret
; CHECK: ret
}
define i32 @test_zextloadi32() {
; CHECK: test_zextloadi32
; CHECK-LABEL: test_zextloadi32
; It's not actually necessary that "ret" is next, but as far as LLVM
; is concerned only 0 or 1 should be loadable so no extension is
; necessary.
%val = load i1* @var
%ret = zext i1 %val to i32
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
ret i32 %ret
; CHECK-NEXT: ret
}
define i64 @test_zextloadi64() {
; CHECK: test_zextloadi64
; CHECK-LABEL: test_zextloadi64
; It's not actually necessary that "ret" is next, but as far as LLVM
; is concerned only 0 or 1 should be loadable so no extension is
; necessary.
%val = load i1* @var
%ret = zext i1 %val to i64
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var]
; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
ret i64 %ret
; CHECK-NEXT: ret

3
test/CodeGen/AArch64/breg.ll
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@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
@stored_label = global i8* null
@ -7,7 +8,7 @@ define void @foo() {
%lab = load i8** @stored_label
indirectbr i8* %lab, [label %otherlab, label %retlab]
; CHECK: adrp {{x[0-9]+}}, stored_label
; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:stored_label]
; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:stored_label]
; CHECK: br {{x[0-9]+}}
otherlab:

11
test/CodeGen/AArch64/callee-save.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s --check-prefix=CHECK-ARM64
@var = global float 0.0
@ -10,6 +11,11 @@ define void @foo() {
; CHECK: stp d10, d11, [sp
; CHECK: stp d8, d9, [sp
; CHECK-ARM64: stp d15, d14, [sp
; CHECK-ARM64: stp d13, d12, [sp
; CHECK-ARM64: stp d11, d10, [sp
; CHECK-ARM64: stp d9, d8, [sp
; Create lots of live variables to exhaust the supply of
; caller-saved registers
%val1 = load volatile float* @var
@ -82,5 +88,10 @@ define void @foo() {
; CHECK: ldp d10, d11, [sp
; CHECK: ldp d12, d13, [sp
; CHECK: ldp d14, d15, [sp
; CHECK-ARM64: ldp d9, d8, [sp
; CHECK-ARM64: ldp d11, d10, [sp
; CHECK-ARM64: ldp d13, d12, [sp
; CHECK-ARM64: ldp d15, d14, [sp
ret void
}

1
test/CodeGen/AArch64/code-model-large-abs.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large < %s | FileCheck %s
; RUN: llc -mtriple=arm64 -code-model=large -o - %s | FileCheck %s
@var8 = global i8 0
@var16 = global i16 0

1
test/CodeGen/AArch64/compare-branch.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0