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Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen.

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This fixes 483.xalancbmk (with tail call opt).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95280 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-02-04 02:40:39 +00:00
parent 76706584c2
commit dcea16313d
1 changed files with 14 additions and 15 deletions
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27
lib/Target/X86/X86ISelLowering.cpp
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@ -1196,13 +1196,11 @@ X86TargetLowering::LowerReturn(SDValue Chain,
RVLocs, *DAG.getContext()); RVLocs, *DAG.getContext());
CCInfo.AnalyzeReturn(Outs, RetCC_X86); CCInfo.AnalyzeReturn(Outs, RetCC_X86);
// If this is the first return lowered for this function, add the regs to the // Add the regs to the liveout set for the function.
// liveout set for the function. MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
for (unsigned i = 0; i != RVLocs.size(); ++i) for (unsigned i = 0; i != RVLocs.size(); ++i)
if (RVLocs[i].isRegLoc()) if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); MRI.addLiveOut(RVLocs[i].getLocReg());
}
SDValue Flag; SDValue Flag;
@ -1255,7 +1253,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
unsigned Reg = FuncInfo->getSRetReturnReg(); unsigned Reg = FuncInfo->getSRetReturnReg();
if (!Reg) { if (!Reg) {
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg); FuncInfo->setSRetReturnReg(Reg);
} }
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
@ -1264,7 +1262,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
Flag = Chain.getValue(1); Flag = Chain.getValue(1);
// RAX now acts like a return value. // RAX now acts like a return value.
MF.getRegInfo().addLiveOut(X86::RAX); MRI.addLiveOut(X86::RAX);
} }
RetOps[0] = Chain; // Update chain. RetOps[0] = Chain; // Update chain.
@ -2097,14 +2095,15 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
} }
if (isTailCall && !WasGlobalOrExternal) { if (isTailCall && !WasGlobalOrExternal) {
unsigned Opc = Is64Bit ? X86::R11 : X86::EAX; // Force the address into a (call preserved) caller-saved register since
// tailcall must happen after callee-saved registers are poped.
// FIXME: Give it a special register class that contains caller-saved
// register instead?
unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
Chain = DAG.getCopyToReg(Chain, dl, Chain = DAG.getCopyToReg(Chain, dl,
DAG.getRegister(Opc, getPointerTy()), DAG.getRegister(TCReg, getPointerTy()),
Callee,InFlag); Callee,InFlag);
Callee = DAG.getRegister(Opc, getPointerTy()); Callee = DAG.getRegister(TCReg, getPointerTy());
// Add register as live out.
MF.getRegInfo().addLiveOut(Opc);
} }
// Returns a chain & a flag for retval copy to use. // Returns a chain & a flag for retval copy to use.