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* Set the is64bit boolean flag in PowerPCRegisterInfo
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class * Use double-word loads and stores for restoring from/saving to stack * Do not allocate R2 if compiling for AIX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15670 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -77,13 +77,13 @@ def TBU : SPR<5>;
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// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
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def GPRC :
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RegisterClass<i32, 4,
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[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
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[R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
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R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R13, R0, R1, LR]>
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R16, R15, R14, R13, R0, R2, R1, LR]>
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{
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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return end()-3;
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return end() - (AIX ? 4 : 3);
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}
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}];
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}
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@ -30,9 +30,14 @@
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#include <iostream>
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using namespace llvm;
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PowerPCRegisterInfo::PowerPCRegisterInfo()
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: PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN,
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PPC::ADJCALLSTACKUP) {}
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namespace llvm {
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// Switch toggling compilation for AIX
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extern cl::opt<bool> AIX;
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}
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PowerPCRegisterInfo::PowerPCRegisterInfo(bool is64b)
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: PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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is64bit(is64b) {}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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if (RC == PowerPC::GPRCRegisterClass) {
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@ -41,12 +46,13 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 8: return 3;
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}
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} else if (RC == PowerPC::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 3;
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case 8: return 4;
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case 4: return 4;
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case 8: return 5;
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}
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}
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std::cerr << "Invalid register class to getIdx()!\n";
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@ -59,7 +65,7 @@ PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] = {
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PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
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PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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if (SrcReg == PPC::LR) {
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@ -78,7 +84,7 @@ PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] = {
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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if (DestReg == PPC::LR) {
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@ -221,17 +227,19 @@ void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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// adjust stack pointer: r1 -= numbytes
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if (NumBytes <= 32768) {
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MI = BuildMI(PPC::STWU, 3).addReg(PPC::R1).addSImm(-NumBytes)
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unsigned StoreOpcode = is64bit ? PPC::STDU : PPC::STWU;
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MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addSImm(-NumBytes)
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.addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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} else {
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int NegNumbytes = -NumBytes;
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unsigned StoreOpcode = is64bit ? PPC::STDUX : PPC::STWUX;
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MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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.addImm(NegNumbytes & 0xFFFF);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
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MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addReg(PPC::R1)
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.addReg(PPC::R0);
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MBB.insert(MBBI, MI);
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}
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@ -249,7 +257,8 @@ void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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unsigned NumBytes = MFI->getStackSize();
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if (NumBytes != 0) {
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MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
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unsigned Opcode = is64bit ? PPC::LD : PPC::LWZ;
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MI = BuildMI(Opcode, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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}
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}
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@ -259,9 +268,10 @@ void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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const TargetRegisterClass*
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PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::LongTyID:
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case Type::ULongTyID:
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if (!is64bit) assert(0 && "Long values can't fit in registers!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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@ -270,7 +280,7 @@ PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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@ -21,8 +21,10 @@ namespace llvm {
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class Type;
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struct PowerPCRegisterInfo : public PowerPCGenRegisterInfo {
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PowerPCRegisterInfo();
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class PowerPCRegisterInfo : public PowerPCGenRegisterInfo {
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bool is64bit;
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public:
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PowerPCRegisterInfo(bool is64b);
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const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
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/// Code Generation virtual methods...
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