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Track IR ordering of SelectionDAG nodes 3/4.

Browse Source 
Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2013-05-25 03:08:10 +00:00
parent ac6d9bec67
commit dd0fb018a7
17 changed files with 31 additions and 190 deletions
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41
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -938,19 +938,13 @@ SDValue SelectionDAGBuilder::getControlRoot() {
return Root;
}
void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
DAG.AssignOrdering(Node, SDNodeOrder);
for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
AssignOrderingToNode(Node->getOperand(I).getNode());
}
void SelectionDAGBuilder::visit(const Instruction &I) {
// Set up outgoing PHI node register values before emitting the terminator.
if (isa<TerminatorInst>(&I))
HandlePHINodesInSuccessorBlocks(I.getParent());
++SDNodeOrder;
CurInst = &I;
visit(I.getOpcode(), I);
@ -975,12 +969,6 @@ void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
#include "llvm/IR/Instruction.def"
}
// Assign the ordering to the freshly created DAG nodes.
if (NodeMap.count(&I)) {
++SDNodeOrder;
AssignOrderingToNode(getValue(&I).getNode());
}
}
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
@ -3397,8 +3385,6 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
++SDNodeOrder;
AssignOrderingToNode(StoreNode.getNode());
DAG.setRoot(StoreNode);
}
@ -3652,12 +3638,6 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
}
setValue(&I, Result);
} else {
// Assign order to result here. If the intrinsic does not produce a result,
// it won't be mapped to a SDNode and visit() will not assign it an order
// number.
++SDNodeOrder;
AssignOrderingToNode(Result.getNode());
}
}
@ -4525,12 +4505,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
return 0;
}
// Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
// but do not always have a corresponding SDNode built. The SDNodeOrder
// absolute, but not relative, values are different depending on whether
// debug info exists.
++SDNodeOrder;
// Check if address has undef value.
if (isa<UndefValue>(Address) ||
(Address->use_empty() && !isa<Argument>(Address))) {
@ -4610,11 +4584,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
if (!V)
return 0;
// Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
// but do not always have a corresponding SDNode built. The SDNodeOrder
// absolute, but not relative, values are different depending on whether
// debug info exists.
++SDNodeOrder;
SDDbgValue *SDV;
if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
@ -5347,18 +5316,12 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
&Values[0], Values.size()));
}
// Assign order to nodes here. If the call does not produce a result, it won't
// be mapped to a SDNode and visit() will not assign it an order number.
if (!Result.second.getNode()) {
// As a special case, a null chain means that a tail call has been emitted and
// the DAG root is already updated.
HasTailCall = true;
++SDNodeOrder;
AssignOrderingToNode(DAG.getRoot().getNode());
} else {
DAG.setRoot(Result.second);
++SDNodeOrder;
AssignOrderingToNode(Result.second.getNode());
}
if (LandingPad) {