mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Lots of code cleanups, no functional changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1650 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
3801f6d383
commit
dd1e40b4ce
@ -12,6 +12,7 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include <iostream>
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#include <iostream>
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@ -56,34 +57,27 @@ PhyRegAlloc::PhyRegAlloc(Method *M,
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// Destructor: Deletes register classes
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// Destructor: Deletes register classes
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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PhyRegAlloc::~PhyRegAlloc() {
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PhyRegAlloc::~PhyRegAlloc() {
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++) {
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delete RegClassList[rc];
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RegClass *RC = RegClassList[rc];
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delete RC;
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}
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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void PhyRegAlloc::createIGNodeListsAndIGs() {
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{
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if (DEBUG_RA) cerr << "Creating LR lists ...\n";
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if(DEBUG_RA ) cerr << "Creating LR lists ...\n";
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// hash map iterator
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
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// hash map end
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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for (; HMI != HMIEnd ; ++HMI ) {
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if (HMI->first) {
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if( (*HMI).first ) {
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LiveRange *L = HMI->second; // get the LiveRange
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if (!L) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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if( !L) {
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if( DEBUG_RA) {
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if( DEBUG_RA) {
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cerr << "\n*?!?Warning: Null liver range found for: ";
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cerr << "\n*?!?Warning: Null liver range found for: ";
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printValue(HMI->first); cerr << "\n";
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printValue(HMI->first); cerr << "\n";
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@ -93,19 +87,17 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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// if the Value * is not null, and LR
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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RegClass *const RC = // RegClass of first value in the LR
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//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
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RegClassList[ L->getRegClass()->getID() ];
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RegClassList[ L->getRegClass()->getID() ];
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RC-> addLRToIG( L ); // add this LR to an IG
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RC->addLRToIG(L); // add this LR to an IG
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}
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}
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}
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}
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}
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}
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// init RegClassList
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->createInterferenceGraph();
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RegClassList[rc]->createInterferenceGraph();
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if( DEBUG_RA)
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if( DEBUG_RA)
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cerr << "LRLists Created!\n";
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cerr << "LRLists Created!\n";
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@ -151,33 +143,26 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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// LROfVar can be null if it is a const since a const
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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// doesn't have a dominating def - see Assumptions above
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//
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//
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if( LROfVar) {
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if (LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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continue;
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// if 2 reg classes are the same set interference
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// if 2 reg classes are the same set interference
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//
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//
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if( RCOfDef == LROfVar->getRegClass() ){
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if(RCOfDef == LROfVar->getRegClass()) {
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RCOfDef->setInterference( LROfDef, LROfVar);
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RCOfDef->setInterference( LROfDef, LROfVar);
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} else if(DEBUG_RA > 1) {
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}
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else if(DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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// instruction stream (e.g., constants)
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cerr << " warning: no live range for " ;
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cerr << " warning: no live range for " ;
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printValue(*LIt); cerr << "\n"; }
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printValue(*LIt); cerr << "\n";
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}
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}
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}
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}
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}
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// For a call instruction, this method sets the CallInterference flag in
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// For a call instruction, this method sets the CallInterference flag in
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// the LR of each variable live int the Live Variable Set live after the
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// the LR of each variable live int the Live Variable Set live after the
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@ -307,7 +292,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// if there are multiple defs in this instruction e.g. in SETX
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// if there are multiple defs in this instruction e.g. in SETX
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//
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//
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if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) )
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if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
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addInterf4PseudoInstr(MInst);
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addInterf4PseudoInstr(MInst);
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@ -449,14 +434,14 @@ void PhyRegAlloc::updateMachineCode()
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unsigned Opcode = MInst->getOpCode();
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unsigned Opcode = MInst->getOpCode();
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// do not process Phis
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// do not process Phis
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if( (TM.getInstrInfo()).isPhi( Opcode ) )
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if (TM.getInstrInfo().isPhi(Opcode))
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continue;
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continue;
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// Now insert speical instructions (if necessary) for call/return
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// Now insert speical instructions (if necessary) for call/return
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// instructions.
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// instructions.
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//
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//
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if( (TM.getInstrInfo()).isCall( Opcode) ||
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if (TM.getInstrInfo().isCall(Opcode) ||
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(TM.getInstrInfo()).isReturn( Opcode) ) {
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TM.getInstrInfo().isReturn(Opcode)) {
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AddedInstrns *AI = AddedInstrMap[ MInst];
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AddedInstrns *AI = AddedInstrMap[ MInst];
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if ( !AI ) {
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if ( !AI ) {
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@ -469,12 +454,10 @@ void PhyRegAlloc::updateMachineCode()
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//
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//
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mcInfo.popAllTempValues(TM);
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mcInfo.popAllTempValues(TM);
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if( (TM.getInstrInfo()).isCall( Opcode ) )
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if (TM.getInstrInfo().isCall(Opcode))
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MRI.colorCallArgs( MInst, LRI, AI, *this, *BBI );
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MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
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else if (TM.getInstrInfo().isReturn(Opcode))
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else if ( (TM.getInstrInfo()).isReturn(Opcode) )
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MRI.colorRetValue(MInst, LRI, AI);
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MRI.colorRetValue( MInst, LRI, AI );
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}
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}
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@ -586,8 +569,8 @@ void PhyRegAlloc::updateMachineCode()
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// If there are instructions to be added *after* this machine
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// If there are instructions to be added *after* this machine
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// instruction, add them now
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// instruction, add them now
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//
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//
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if( AddedInstrMap[ MInst ] &&
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if(AddedInstrMap[MInst] &&
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! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
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!AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
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// if there are delay slots for this instruction, the instructions
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// if there are delay slots for this instruction, the instructions
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// added after it must really go after the delayed instruction(s)
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// added after it must really go after the delayed instruction(s)
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@ -595,7 +578,7 @@ void PhyRegAlloc::updateMachineCode()
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// corresponding delayed instruction
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// corresponding delayed instruction
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unsigned delay;
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unsigned delay;
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if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
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if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
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move2DelayedInstr(MInst, *(MInstIterator+delay) );
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move2DelayedInstr(MInst, *(MInstIterator+delay) );
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if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
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if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
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@ -689,13 +672,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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// actual loading instruction
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// actual loading instruction
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AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
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AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
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if( MIBef )
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if(MIBef)
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(AI->InstrnsBefore).push_back(MIBef);
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AI->InstrnsBefore.push_back(MIBef);
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(AI->InstrnsBefore).push_back(AdIMid);
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AI->InstrnsBefore.push_back(AdIMid);
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if( MIAft)
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if(MIAft)
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(AI->InstrnsAfter).push_front(MIAft);
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AI->InstrnsAfter.push_front(MIAft);
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}
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}
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@ -707,13 +690,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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// actual storing instruction
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// actual storing instruction
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AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
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AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
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if( MIBef )
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if (MIBef)
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(AI->InstrnsBefore).push_back(MIBef);
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AI->InstrnsBefore.push_back(MIBef);
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(AI->InstrnsAfter).push_front(AdIMid);
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AI->InstrnsAfter.push_front(AdIMid);
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if( MIAft)
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if (MIAft)
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(AI->InstrnsAfter).push_front(MIAft);
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AI->InstrnsAfter.push_front(MIAft);
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} // if !DEF
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} // if !DEF
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@ -1080,16 +1063,13 @@ void PhyRegAlloc::colorCallRetArgs()
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if( (TM.getInstrInfo()).isCall( OpCode ) )
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if (TM.getInstrInfo().isCall(OpCode))
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MRI.colorCallArgs( CRMI, LRI, AI, *this );
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MRI.colorCallArgs(CRMI, LRI, AI, *this);
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else if (TM.getInstrInfo().isReturn(OpCode))
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else if ( (TM.getInstrInfo()).isReturn(OpCode) )
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MRI.colorRetValue( CRMI, LRI, AI );
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MRI.colorRetValue( CRMI, LRI, AI );
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else
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else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
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assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
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}
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}
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}
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}
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#endif
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#endif
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@ -1100,16 +1080,14 @@ void PhyRegAlloc::colorCallRetArgs()
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void PhyRegAlloc::colorIncomingArgs()
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void PhyRegAlloc::colorIncomingArgs()
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{
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{
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const BasicBlock *const FirstBB = Meth->front();
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const BasicBlock *const FirstBB = Meth->front();
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const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
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const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
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assert( FirstMI && "No machine instruction in entry BB");
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assert(FirstMI && "No machine instruction in entry BB");
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AddedInstrns *AI = AddedInstrMap[ FirstMI ];
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AddedInstrns *AI = AddedInstrMap[FirstMI];
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if (!AI) {
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if (!AI)
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AI = new AddedInstrns();
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AddedInstrMap[FirstMI] = AI = new AddedInstrns();
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AddedInstrMap[FirstMI] = AI;
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}
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MRI.colorMethodArgs(Meth, LRI, AI );
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MRI.colorMethodArgs(Meth, LRI, AI);
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}
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}
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@ -1139,16 +1117,12 @@ void PhyRegAlloc::markUnusableSugColors()
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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for(; HMI != HMIEnd ; ++HMI ) {
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if (HMI->first) {
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if( (*HMI).first ) {
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LiveRange *L = HMI->second; // get the LiveRange
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if (L) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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if(L->hasSuggestedColor()) {
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int RCID = L->getRegClass()->getID();
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if(L) {
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if( L->hasSuggestedColor() ) {
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int RCID = (L->getRegClass())->getID();
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if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
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if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
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L->isCallInterference() )
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L->isCallInterference() )
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L->setSuggestedColorUsable( false );
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L->setSuggestedColorUsable( false );
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@ -1202,7 +1176,7 @@ void PhyRegAlloc::allocateRegisters()
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//
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//
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LRI.constructLiveRanges(); // create LR info
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LRI.constructLiveRanges(); // create LR info
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if( DEBUG_RA )
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if (DEBUG_RA)
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LRI.printLiveRanges();
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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@ -1210,7 +1184,7 @@ void PhyRegAlloc::allocateRegisters()
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buildInterferenceGraphs(); // build IGs in all reg classes
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA ) {
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if (DEBUG_RA) {
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// print all LRs in all reg classes
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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RegClassList[ rc ]->printIGNodeList();
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@ -1257,19 +1231,16 @@ void PhyRegAlloc::allocateRegisters()
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//
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//
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colorIncomingArgs();
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colorIncomingArgs();
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// Now update the machine code with register names and add any
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// Now update the machine code with register names and add any
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// additional code inserted by the register allocator to the instruction
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// additional code inserted by the register allocator to the instruction
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// stream
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// stream
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//
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//
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updateMachineCode();
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updateMachineCode();
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if (DEBUG_RA) {
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if (DEBUG_RA) {
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MachineCodeForMethod::get(Meth).dump();
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MachineCodeForMethod::get(Meth).dump();
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printMachineCode(); // only for DEBUGGING
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printMachineCode(); // only for DEBUGGING
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}
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}
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}
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}
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@ -12,6 +12,7 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include <iostream>
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#include <iostream>
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@ -56,34 +57,27 @@ PhyRegAlloc::PhyRegAlloc(Method *M,
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// Destructor: Deletes register classes
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// Destructor: Deletes register classes
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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PhyRegAlloc::~PhyRegAlloc() {
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PhyRegAlloc::~PhyRegAlloc() {
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++) {
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delete RegClassList[rc];
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RegClass *RC = RegClassList[rc];
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delete RC;
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}
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// This method initally creates interference graphs (one in each reg class)
|
||||||
// and IGNodeList (one in each IG). The actual nodes will be pushed later.
|
// and IGNodeList (one in each IG). The actual nodes will be pushed later.
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
void PhyRegAlloc::createIGNodeListsAndIGs()
|
void PhyRegAlloc::createIGNodeListsAndIGs() {
|
||||||
{
|
if (DEBUG_RA) cerr << "Creating LR lists ...\n";
|
||||||
if(DEBUG_RA ) cerr << "Creating LR lists ...\n";
|
|
||||||
|
|
||||||
// hash map iterator
|
// hash map iterator
|
||||||
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
|
||||||
|
|
||||||
// hash map end
|
// hash map end
|
||||||
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
|
||||||
|
|
||||||
for( ; HMI != HMIEnd ; ++HMI ) {
|
for (; HMI != HMIEnd ; ++HMI ) {
|
||||||
|
if (HMI->first) {
|
||||||
if( (*HMI).first ) {
|
LiveRange *L = HMI->second; // get the LiveRange
|
||||||
|
if (!L) {
|
||||||
LiveRange *L = (*HMI).second; // get the LiveRange
|
|
||||||
|
|
||||||
if( !L) {
|
|
||||||
if( DEBUG_RA) {
|
if( DEBUG_RA) {
|
||||||
cerr << "\n*?!?Warning: Null liver range found for: ";
|
cerr << "\n*?!?Warning: Null liver range found for: ";
|
||||||
printValue(HMI->first); cerr << "\n";
|
printValue(HMI->first); cerr << "\n";
|
||||||
@ -93,19 +87,17 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
|
|||||||
// if the Value * is not null, and LR
|
// if the Value * is not null, and LR
|
||||||
// is not yet written to the IGNodeList
|
// is not yet written to the IGNodeList
|
||||||
if( !(L->getUserIGNode()) ) {
|
if( !(L->getUserIGNode()) ) {
|
||||||
|
|
||||||
RegClass *const RC = // RegClass of first value in the LR
|
RegClass *const RC = // RegClass of first value in the LR
|
||||||
//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
|
|
||||||
RegClassList[ L->getRegClass()->getID() ];
|
RegClassList[ L->getRegClass()->getID() ];
|
||||||
|
|
||||||
RC-> addLRToIG( L ); // add this LR to an IG
|
RC->addLRToIG(L); // add this LR to an IG
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// init RegClassList
|
// init RegClassList
|
||||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||||
RegClassList[ rc ]->createInterferenceGraph();
|
RegClassList[rc]->createInterferenceGraph();
|
||||||
|
|
||||||
if( DEBUG_RA)
|
if( DEBUG_RA)
|
||||||
cerr << "LRLists Created!\n";
|
cerr << "LRLists Created!\n";
|
||||||
@ -151,33 +143,26 @@ void PhyRegAlloc::addInterference(const Value *const Def,
|
|||||||
// LROfVar can be null if it is a const since a const
|
// LROfVar can be null if it is a const since a const
|
||||||
// doesn't have a dominating def - see Assumptions above
|
// doesn't have a dominating def - see Assumptions above
|
||||||
//
|
//
|
||||||
if( LROfVar) {
|
if (LROfVar) {
|
||||||
|
|
||||||
if(LROfDef == LROfVar) // do not set interf for same LR
|
if(LROfDef == LROfVar) // do not set interf for same LR
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
// if 2 reg classes are the same set interference
|
// if 2 reg classes are the same set interference
|
||||||
//
|
//
|
||||||
if( RCOfDef == LROfVar->getRegClass() ){
|
if(RCOfDef == LROfVar->getRegClass()) {
|
||||||
RCOfDef->setInterference( LROfDef, LROfVar);
|
RCOfDef->setInterference( LROfDef, LROfVar);
|
||||||
|
} else if(DEBUG_RA > 1) {
|
||||||
}
|
|
||||||
|
|
||||||
else if(DEBUG_RA > 1) {
|
|
||||||
// we will not have LRs for values not explicitly allocated in the
|
// we will not have LRs for values not explicitly allocated in the
|
||||||
// instruction stream (e.g., constants)
|
// instruction stream (e.g., constants)
|
||||||
cerr << " warning: no live range for " ;
|
cerr << " warning: no live range for " ;
|
||||||
printValue(*LIt); cerr << "\n"; }
|
printValue(*LIt); cerr << "\n";
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
||||||
// For a call instruction, this method sets the CallInterference flag in
|
// For a call instruction, this method sets the CallInterference flag in
|
||||||
// the LR of each variable live int the Live Variable Set live after the
|
// the LR of each variable live int the Live Variable Set live after the
|
||||||
@ -307,7 +292,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
|
|||||||
|
|
||||||
// if there are multiple defs in this instruction e.g. in SETX
|
// if there are multiple defs in this instruction e.g. in SETX
|
||||||
//
|
//
|
||||||
if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) )
|
if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
|
||||||
addInterf4PseudoInstr(MInst);
|
addInterf4PseudoInstr(MInst);
|
||||||
|
|
||||||
|
|
||||||
@ -449,14 +434,14 @@ void PhyRegAlloc::updateMachineCode()
|
|||||||
unsigned Opcode = MInst->getOpCode();
|
unsigned Opcode = MInst->getOpCode();
|
||||||
|
|
||||||
// do not process Phis
|
// do not process Phis
|
||||||
if( (TM.getInstrInfo()).isPhi( Opcode ) )
|
if (TM.getInstrInfo().isPhi(Opcode))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
// Now insert speical instructions (if necessary) for call/return
|
// Now insert speical instructions (if necessary) for call/return
|
||||||
// instructions.
|
// instructions.
|
||||||
//
|
//
|
||||||
if( (TM.getInstrInfo()).isCall( Opcode) ||
|
if (TM.getInstrInfo().isCall(Opcode) ||
|
||||||
(TM.getInstrInfo()).isReturn( Opcode) ) {
|
TM.getInstrInfo().isReturn(Opcode)) {
|
||||||
|
|
||||||
AddedInstrns *AI = AddedInstrMap[ MInst];
|
AddedInstrns *AI = AddedInstrMap[ MInst];
|
||||||
if ( !AI ) {
|
if ( !AI ) {
|
||||||
@ -469,12 +454,10 @@ void PhyRegAlloc::updateMachineCode()
|
|||||||
//
|
//
|
||||||
mcInfo.popAllTempValues(TM);
|
mcInfo.popAllTempValues(TM);
|
||||||
|
|
||||||
if( (TM.getInstrInfo()).isCall( Opcode ) )
|
if (TM.getInstrInfo().isCall(Opcode))
|
||||||
MRI.colorCallArgs( MInst, LRI, AI, *this, *BBI );
|
MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
|
||||||
|
else if (TM.getInstrInfo().isReturn(Opcode))
|
||||||
else if ( (TM.getInstrInfo()).isReturn(Opcode) )
|
MRI.colorRetValue(MInst, LRI, AI);
|
||||||
MRI.colorRetValue( MInst, LRI, AI );
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -586,8 +569,8 @@ void PhyRegAlloc::updateMachineCode()
|
|||||||
// If there are instructions to be added *after* this machine
|
// If there are instructions to be added *after* this machine
|
||||||
// instruction, add them now
|
// instruction, add them now
|
||||||
//
|
//
|
||||||
if( AddedInstrMap[ MInst ] &&
|
if(AddedInstrMap[MInst] &&
|
||||||
! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
|
!AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
|
||||||
|
|
||||||
// if there are delay slots for this instruction, the instructions
|
// if there are delay slots for this instruction, the instructions
|
||||||
// added after it must really go after the delayed instruction(s)
|
// added after it must really go after the delayed instruction(s)
|
||||||
@ -595,7 +578,7 @@ void PhyRegAlloc::updateMachineCode()
|
|||||||
// corresponding delayed instruction
|
// corresponding delayed instruction
|
||||||
|
|
||||||
unsigned delay;
|
unsigned delay;
|
||||||
if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
||||||
move2DelayedInstr(MInst, *(MInstIterator+delay) );
|
move2DelayedInstr(MInst, *(MInstIterator+delay) );
|
||||||
|
|
||||||
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
|
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
|
||||||
@ -689,13 +672,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|||||||
// actual loading instruction
|
// actual loading instruction
|
||||||
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
|
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
|
||||||
|
|
||||||
if( MIBef )
|
if(MIBef)
|
||||||
(AI->InstrnsBefore).push_back(MIBef);
|
AI->InstrnsBefore.push_back(MIBef);
|
||||||
|
|
||||||
(AI->InstrnsBefore).push_back(AdIMid);
|
AI->InstrnsBefore.push_back(AdIMid);
|
||||||
|
|
||||||
if( MIAft)
|
if(MIAft)
|
||||||
(AI->InstrnsAfter).push_front(MIAft);
|
AI->InstrnsAfter.push_front(MIAft);
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
@ -707,13 +690,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|||||||
// actual storing instruction
|
// actual storing instruction
|
||||||
AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
|
AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
|
||||||
|
|
||||||
if( MIBef )
|
if (MIBef)
|
||||||
(AI->InstrnsBefore).push_back(MIBef);
|
AI->InstrnsBefore.push_back(MIBef);
|
||||||
|
|
||||||
(AI->InstrnsAfter).push_front(AdIMid);
|
AI->InstrnsAfter.push_front(AdIMid);
|
||||||
|
|
||||||
if( MIAft)
|
if (MIAft)
|
||||||
(AI->InstrnsAfter).push_front(MIAft);
|
AI->InstrnsAfter.push_front(MIAft);
|
||||||
|
|
||||||
} // if !DEF
|
} // if !DEF
|
||||||
|
|
||||||
@ -1080,16 +1063,13 @@ void PhyRegAlloc::colorCallRetArgs()
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
if( (TM.getInstrInfo()).isCall( OpCode ) )
|
if (TM.getInstrInfo().isCall(OpCode))
|
||||||
MRI.colorCallArgs( CRMI, LRI, AI, *this );
|
MRI.colorCallArgs(CRMI, LRI, AI, *this);
|
||||||
|
else if (TM.getInstrInfo().isReturn(OpCode))
|
||||||
else if ( (TM.getInstrInfo()).isReturn(OpCode) )
|
|
||||||
MRI.colorRetValue( CRMI, LRI, AI );
|
MRI.colorRetValue( CRMI, LRI, AI );
|
||||||
|
else
|
||||||
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
|
assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
@ -1100,16 +1080,14 @@ void PhyRegAlloc::colorCallRetArgs()
|
|||||||
void PhyRegAlloc::colorIncomingArgs()
|
void PhyRegAlloc::colorIncomingArgs()
|
||||||
{
|
{
|
||||||
const BasicBlock *const FirstBB = Meth->front();
|
const BasicBlock *const FirstBB = Meth->front();
|
||||||
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
|
const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
|
||||||
assert( FirstMI && "No machine instruction in entry BB");
|
assert(FirstMI && "No machine instruction in entry BB");
|
||||||
|
|
||||||
AddedInstrns *AI = AddedInstrMap[ FirstMI ];
|
AddedInstrns *AI = AddedInstrMap[FirstMI];
|
||||||
if (!AI) {
|
if (!AI)
|
||||||
AI = new AddedInstrns();
|
AddedInstrMap[FirstMI] = AI = new AddedInstrns();
|
||||||
AddedInstrMap[FirstMI] = AI;
|
|
||||||
}
|
|
||||||
|
|
||||||
MRI.colorMethodArgs(Meth, LRI, AI );
|
MRI.colorMethodArgs(Meth, LRI, AI);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -1139,16 +1117,12 @@ void PhyRegAlloc::markUnusableSugColors()
|
|||||||
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
||||||
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
||||||
|
|
||||||
for( ; HMI != HMIEnd ; ++HMI ) {
|
for(; HMI != HMIEnd ; ++HMI ) {
|
||||||
|
if (HMI->first) {
|
||||||
if( (*HMI).first ) {
|
LiveRange *L = HMI->second; // get the LiveRange
|
||||||
|
if (L) {
|
||||||
LiveRange *L = (*HMI).second; // get the LiveRange
|
if(L->hasSuggestedColor()) {
|
||||||
|
int RCID = L->getRegClass()->getID();
|
||||||
if(L) {
|
|
||||||
if( L->hasSuggestedColor() ) {
|
|
||||||
|
|
||||||
int RCID = (L->getRegClass())->getID();
|
|
||||||
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
||||||
L->isCallInterference() )
|
L->isCallInterference() )
|
||||||
L->setSuggestedColorUsable( false );
|
L->setSuggestedColorUsable( false );
|
||||||
@ -1202,7 +1176,7 @@ void PhyRegAlloc::allocateRegisters()
|
|||||||
//
|
//
|
||||||
LRI.constructLiveRanges(); // create LR info
|
LRI.constructLiveRanges(); // create LR info
|
||||||
|
|
||||||
if( DEBUG_RA )
|
if (DEBUG_RA)
|
||||||
LRI.printLiveRanges();
|
LRI.printLiveRanges();
|
||||||
|
|
||||||
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
||||||
@ -1210,7 +1184,7 @@ void PhyRegAlloc::allocateRegisters()
|
|||||||
buildInterferenceGraphs(); // build IGs in all reg classes
|
buildInterferenceGraphs(); // build IGs in all reg classes
|
||||||
|
|
||||||
|
|
||||||
if( DEBUG_RA ) {
|
if (DEBUG_RA) {
|
||||||
// print all LRs in all reg classes
|
// print all LRs in all reg classes
|
||||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||||
RegClassList[ rc ]->printIGNodeList();
|
RegClassList[ rc ]->printIGNodeList();
|
||||||
@ -1257,19 +1231,16 @@ void PhyRegAlloc::allocateRegisters()
|
|||||||
//
|
//
|
||||||
colorIncomingArgs();
|
colorIncomingArgs();
|
||||||
|
|
||||||
|
|
||||||
// Now update the machine code with register names and add any
|
// Now update the machine code with register names and add any
|
||||||
// additional code inserted by the register allocator to the instruction
|
// additional code inserted by the register allocator to the instruction
|
||||||
// stream
|
// stream
|
||||||
//
|
//
|
||||||
updateMachineCode();
|
updateMachineCode();
|
||||||
|
|
||||||
|
|
||||||
if (DEBUG_RA) {
|
if (DEBUG_RA) {
|
||||||
MachineCodeForMethod::get(Meth).dump();
|
MachineCodeForMethod::get(Meth).dump();
|
||||||
printMachineCode(); // only for DEBUGGING
|
printMachineCode(); // only for DEBUGGING
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user