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Lots of code cleanups, no functional changes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1650 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-02-03 07:46:34 +00:00
parent 3801f6d383
commit dd1e40b4ce
2 changed files with 146 additions and 204 deletions
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175
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -12,6 +12,7 @@
#include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineFrameInfo.h"
#include <iostream> #include <iostream>
@ -56,56 +57,47 @@ PhyRegAlloc::PhyRegAlloc(Method *M,
// Destructor: Deletes register classes // Destructor: Deletes register classes
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
PhyRegAlloc::~PhyRegAlloc() { PhyRegAlloc::~PhyRegAlloc() {
for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
for( unsigned int rc=0; rc < NumOfRegClasses; rc++) { delete RegClassList[rc];
RegClass *RC = RegClassList[rc];
delete RC;
}
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// This method initally creates interference graphs (one in each reg class) // This method initally creates interference graphs (one in each reg class)
// and IGNodeList (one in each IG). The actual nodes will be pushed later. // and IGNodeList (one in each IG). The actual nodes will be pushed later.
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
void PhyRegAlloc::createIGNodeListsAndIGs() void PhyRegAlloc::createIGNodeListsAndIGs() {
{ if (DEBUG_RA) cerr << "Creating LR lists ...\n";
if(DEBUG_RA ) cerr << "Creating LR lists ...\n";
// hash map iterator // hash map iterator
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
// hash map end // hash map end
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end(); LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
for( ; HMI != HMIEnd ; ++HMI ) { for (; HMI != HMIEnd ; ++HMI ) {
if (HMI->first) {
if( (*HMI).first ) { LiveRange *L = HMI->second; // get the LiveRange
if (!L) {
LiveRange *L = (*HMI).second; // get the LiveRange if( DEBUG_RA) {
cerr << "\n*?!?Warning: Null liver range found for: ";
if( !L) { printValue(HMI->first); cerr << "\n";
if( DEBUG_RA) { }
cerr << "\n*?!?Warning: Null liver range found for: "; continue;
printValue(HMI->first); cerr << "\n"; }
}
continue;
}
// if the Value * is not null, and LR // if the Value * is not null, and LR
// is not yet written to the IGNodeList // is not yet written to the IGNodeList
if( !(L->getUserIGNode()) ) { if( !(L->getUserIGNode()) ) {
RegClass *const RC = // RegClass of first value in the LR
RegClass *const RC = // RegClass of first value in the LR RegClassList[ L->getRegClass()->getID() ];
//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
RegClassList[ L->getRegClass()->getID() ]; RC->addLRToIG(L); // add this LR to an IG
}
RC-> addLRToIG( L ); // add this LR to an IG
}
} }
} }
// init RegClassList // init RegClassList
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++) for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[ rc ]->createInterferenceGraph(); RegClassList[rc]->createInterferenceGraph();
if( DEBUG_RA) if( DEBUG_RA)
cerr << "LRLists Created!\n"; cerr << "LRLists Created!\n";
@ -151,33 +143,26 @@ void PhyRegAlloc::addInterference(const Value *const Def,
// LROfVar can be null if it is a const since a const // LROfVar can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above // doesn't have a dominating def - see Assumptions above
// //
if( LROfVar) { if (LROfVar) {
if(LROfDef == LROfVar) // do not set interf for same LR if(LROfDef == LROfVar) // do not set interf for same LR
continue; continue;
// if 2 reg classes are the same set interference // if 2 reg classes are the same set interference
// //
if( RCOfDef == LROfVar->getRegClass() ){ if(RCOfDef == LROfVar->getRegClass()) {
RCOfDef->setInterference( LROfDef, LROfVar); RCOfDef->setInterference( LROfDef, LROfVar);
} else if(DEBUG_RA > 1) {
// we will not have LRs for values not explicitly allocated in the
// instruction stream (e.g., constants)
cerr << " warning: no live range for " ;
printValue(*LIt); cerr << "\n";
} }
else if(DEBUG_RA > 1) {
// we will not have LRs for values not explicitly allocated in the
// instruction stream (e.g., constants)
cerr << " warning: no live range for " ;
printValue(*LIt); cerr << "\n"; }
} }
} }
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// For a call instruction, this method sets the CallInterference flag in // For a call instruction, this method sets the CallInterference flag in
// the LR of each variable live int the Live Variable Set live after the // the LR of each variable live int the Live Variable Set live after the
@ -307,7 +292,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
// if there are multiple defs in this instruction e.g. in SETX // if there are multiple defs in this instruction e.g. in SETX
// //
if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) ) if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
addInterf4PseudoInstr(MInst); addInterf4PseudoInstr(MInst);
@ -449,14 +434,14 @@ void PhyRegAlloc::updateMachineCode()
unsigned Opcode = MInst->getOpCode(); unsigned Opcode = MInst->getOpCode();
// do not process Phis // do not process Phis
if( (TM.getInstrInfo()).isPhi( Opcode ) ) if (TM.getInstrInfo().isPhi(Opcode))
continue; continue;
// Now insert speical instructions (if necessary) for call/return // Now insert speical instructions (if necessary) for call/return
// instructions. // instructions.
// //
if( (TM.getInstrInfo()).isCall( Opcode) || if (TM.getInstrInfo().isCall(Opcode) ||
(TM.getInstrInfo()).isReturn( Opcode) ) { TM.getInstrInfo().isReturn(Opcode)) {
AddedInstrns *AI = AddedInstrMap[ MInst]; AddedInstrns *AI = AddedInstrMap[ MInst];
if ( !AI ) { if ( !AI ) {
@ -469,12 +454,10 @@ void PhyRegAlloc::updateMachineCode()
// //
mcInfo.popAllTempValues(TM); mcInfo.popAllTempValues(TM);
if( (TM.getInstrInfo()).isCall( Opcode ) ) if (TM.getInstrInfo().isCall(Opcode))
MRI.colorCallArgs( MInst, LRI, AI, *this, *BBI ); MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
else if (TM.getInstrInfo().isReturn(Opcode))
else if ( (TM.getInstrInfo()).isReturn(Opcode) ) MRI.colorRetValue(MInst, LRI, AI);
MRI.colorRetValue( MInst, LRI, AI );
} }
@ -586,8 +569,8 @@ void PhyRegAlloc::updateMachineCode()
// If there are instructions to be added *after* this machine // If there are instructions to be added *after* this machine
// instruction, add them now // instruction, add them now
// //
if( AddedInstrMap[ MInst ] && if(AddedInstrMap[MInst] &&
! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) { !AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
// if there are delay slots for this instruction, the instructions // if there are delay slots for this instruction, the instructions
// added after it must really go after the delayed instruction(s) // added after it must really go after the delayed instruction(s)
@ -595,7 +578,7 @@ void PhyRegAlloc::updateMachineCode()
// corresponding delayed instruction // corresponding delayed instruction
unsigned delay; unsigned delay;
if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){ if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
move2DelayedInstr(MInst, *(MInstIterator+delay) ); move2DelayedInstr(MInst, *(MInstIterator+delay) );
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot"; if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
@ -689,13 +672,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
// actual loading instruction // actual loading instruction
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType); AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
if( MIBef ) if(MIBef)
(AI->InstrnsBefore).push_back(MIBef); AI->InstrnsBefore.push_back(MIBef);
(AI->InstrnsBefore).push_back(AdIMid); AI->InstrnsBefore.push_back(AdIMid);
if( MIAft) if(MIAft)
(AI->InstrnsAfter).push_front(MIAft); AI->InstrnsAfter.push_front(MIAft);
} }
@ -707,13 +690,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
// actual storing instruction // actual storing instruction
AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType); AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
if( MIBef ) if (MIBef)
(AI->InstrnsBefore).push_back(MIBef); AI->InstrnsBefore.push_back(MIBef);
(AI->InstrnsAfter).push_front(AdIMid); AI->InstrnsAfter.push_front(AdIMid);
if( MIAft) if (MIAft)
(AI->InstrnsAfter).push_front(MIAft); AI->InstrnsAfter.push_front(MIAft);
} // if !DEF } // if !DEF
@ -1080,16 +1063,13 @@ void PhyRegAlloc::colorCallRetArgs()
if( (TM.getInstrInfo()).isCall( OpCode ) ) if (TM.getInstrInfo().isCall(OpCode))
MRI.colorCallArgs( CRMI, LRI, AI, *this ); MRI.colorCallArgs(CRMI, LRI, AI, *this);
else if (TM.getInstrInfo().isReturn(OpCode))
else if ( (TM.getInstrInfo()).isReturn(OpCode) )
MRI.colorRetValue( CRMI, LRI, AI ); MRI.colorRetValue( CRMI, LRI, AI );
else
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" ); assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
} }
} }
#endif #endif
@ -1100,16 +1080,14 @@ void PhyRegAlloc::colorCallRetArgs()
void PhyRegAlloc::colorIncomingArgs() void PhyRegAlloc::colorIncomingArgs()
{ {
const BasicBlock *const FirstBB = Meth->front(); const BasicBlock *const FirstBB = Meth->front();
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin()); const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
assert( FirstMI && "No machine instruction in entry BB"); assert(FirstMI && "No machine instruction in entry BB");
AddedInstrns *AI = AddedInstrMap[ FirstMI ]; AddedInstrns *AI = AddedInstrMap[FirstMI];
if (!AI) { if (!AI)
AI = new AddedInstrns(); AddedInstrMap[FirstMI] = AI = new AddedInstrns();
AddedInstrMap[FirstMI] = AI;
}
MRI.colorMethodArgs(Meth, LRI, AI ); MRI.colorMethodArgs(Meth, LRI, AI);
} }
@ -1139,16 +1117,12 @@ void PhyRegAlloc::markUnusableSugColors()
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end(); LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
for( ; HMI != HMIEnd ; ++HMI ) { for(; HMI != HMIEnd ; ++HMI ) {
if (HMI->first) {
if( (*HMI).first ) { LiveRange *L = HMI->second; // get the LiveRange
if (L) {
LiveRange *L = (*HMI).second; // get the LiveRange if(L->hasSuggestedColor()) {
int RCID = L->getRegClass()->getID();
if(L) {
if( L->hasSuggestedColor() ) {
int RCID = (L->getRegClass())->getID();
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) && if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
L->isCallInterference() ) L->isCallInterference() )
L->setSuggestedColorUsable( false ); L->setSuggestedColorUsable( false );
@ -1202,7 +1176,7 @@ void PhyRegAlloc::allocateRegisters()
// //
LRI.constructLiveRanges(); // create LR info LRI.constructLiveRanges(); // create LR info
if( DEBUG_RA ) if (DEBUG_RA)
LRI.printLiveRanges(); LRI.printLiveRanges();
createIGNodeListsAndIGs(); // create IGNode list and IGs createIGNodeListsAndIGs(); // create IGNode list and IGs
@ -1210,7 +1184,7 @@ void PhyRegAlloc::allocateRegisters()
buildInterferenceGraphs(); // build IGs in all reg classes buildInterferenceGraphs(); // build IGs in all reg classes
if( DEBUG_RA ) { if (DEBUG_RA) {
// print all LRs in all reg classes // print all LRs in all reg classes
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++) for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[ rc ]->printIGNodeList(); RegClassList[ rc ]->printIGNodeList();
@ -1257,19 +1231,16 @@ void PhyRegAlloc::allocateRegisters()
// //
colorIncomingArgs(); colorIncomingArgs();
// Now update the machine code with register names and add any // Now update the machine code with register names and add any
// additional code inserted by the register allocator to the instruction // additional code inserted by the register allocator to the instruction
// stream // stream
// //
updateMachineCode(); updateMachineCode();
if (DEBUG_RA) { if (DEBUG_RA) {
MachineCodeForMethod::get(Meth).dump(); MachineCodeForMethod::get(Meth).dump();
printMachineCode(); // only for DEBUGGING printMachineCode(); // only for DEBUGGING
} }
} }

175
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -12,6 +12,7 @@
#include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineFrameInfo.h"
#include <iostream> #include <iostream>
@ -56,56 +57,47 @@ PhyRegAlloc::PhyRegAlloc(Method *M,
// Destructor: Deletes register classes // Destructor: Deletes register classes
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
PhyRegAlloc::~PhyRegAlloc() { PhyRegAlloc::~PhyRegAlloc() {
for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
for( unsigned int rc=0; rc < NumOfRegClasses; rc++) { delete RegClassList[rc];
RegClass *RC = RegClassList[rc];
delete RC;
}
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// This method initally creates interference graphs (one in each reg class) // This method initally creates interference graphs (one in each reg class)
// and IGNodeList (one in each IG). The actual nodes will be pushed later. // and IGNodeList (one in each IG). The actual nodes will be pushed later.
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
void PhyRegAlloc::createIGNodeListsAndIGs() void PhyRegAlloc::createIGNodeListsAndIGs() {
{ if (DEBUG_RA) cerr << "Creating LR lists ...\n";
if(DEBUG_RA ) cerr << "Creating LR lists ...\n";
// hash map iterator // hash map iterator
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
// hash map end // hash map end
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end(); LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
for( ; HMI != HMIEnd ; ++HMI ) { for (; HMI != HMIEnd ; ++HMI ) {
if (HMI->first) {
if( (*HMI).first ) { LiveRange *L = HMI->second; // get the LiveRange
if (!L) {
LiveRange *L = (*HMI).second; // get the LiveRange if( DEBUG_RA) {
cerr << "\n*?!?Warning: Null liver range found for: ";
if( !L) { printValue(HMI->first); cerr << "\n";
if( DEBUG_RA) { }
cerr << "\n*?!?Warning: Null liver range found for: "; continue;
printValue(HMI->first); cerr << "\n"; }
}
continue;
}
// if the Value * is not null, and LR // if the Value * is not null, and LR
// is not yet written to the IGNodeList // is not yet written to the IGNodeList
if( !(L->getUserIGNode()) ) { if( !(L->getUserIGNode()) ) {
RegClass *const RC = // RegClass of first value in the LR
RegClass *const RC = // RegClass of first value in the LR RegClassList[ L->getRegClass()->getID() ];
//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
RegClassList[ L->getRegClass()->getID() ]; RC->addLRToIG(L); // add this LR to an IG
}
RC-> addLRToIG( L ); // add this LR to an IG
}
} }
} }
// init RegClassList // init RegClassList
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++) for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[ rc ]->createInterferenceGraph(); RegClassList[rc]->createInterferenceGraph();
if( DEBUG_RA) if( DEBUG_RA)
cerr << "LRLists Created!\n"; cerr << "LRLists Created!\n";
@ -151,33 +143,26 @@ void PhyRegAlloc::addInterference(const Value *const Def,
// LROfVar can be null if it is a const since a const // LROfVar can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above // doesn't have a dominating def - see Assumptions above
// //
if( LROfVar) { if (LROfVar) {
if(LROfDef == LROfVar) // do not set interf for same LR if(LROfDef == LROfVar) // do not set interf for same LR
continue; continue;
// if 2 reg classes are the same set interference // if 2 reg classes are the same set interference
// //
if( RCOfDef == LROfVar->getRegClass() ){ if(RCOfDef == LROfVar->getRegClass()) {
RCOfDef->setInterference( LROfDef, LROfVar); RCOfDef->setInterference( LROfDef, LROfVar);
} else if(DEBUG_RA > 1) {
// we will not have LRs for values not explicitly allocated in the
// instruction stream (e.g., constants)
cerr << " warning: no live range for " ;
printValue(*LIt); cerr << "\n";
} }
else if(DEBUG_RA > 1) {
// we will not have LRs for values not explicitly allocated in the
// instruction stream (e.g., constants)
cerr << " warning: no live range for " ;
printValue(*LIt); cerr << "\n"; }
} }
} }
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// For a call instruction, this method sets the CallInterference flag in // For a call instruction, this method sets the CallInterference flag in
// the LR of each variable live int the Live Variable Set live after the // the LR of each variable live int the Live Variable Set live after the
@ -307,7 +292,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
// if there are multiple defs in this instruction e.g. in SETX // if there are multiple defs in this instruction e.g. in SETX
// //
if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) ) if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
addInterf4PseudoInstr(MInst); addInterf4PseudoInstr(MInst);
@ -449,14 +434,14 @@ void PhyRegAlloc::updateMachineCode()
unsigned Opcode = MInst->getOpCode(); unsigned Opcode = MInst->getOpCode();
// do not process Phis // do not process Phis
if( (TM.getInstrInfo()).isPhi( Opcode ) ) if (TM.getInstrInfo().isPhi(Opcode))
continue; continue;
// Now insert speical instructions (if necessary) for call/return // Now insert speical instructions (if necessary) for call/return
// instructions. // instructions.
// //
if( (TM.getInstrInfo()).isCall( Opcode) || if (TM.getInstrInfo().isCall(Opcode) ||
(TM.getInstrInfo()).isReturn( Opcode) ) { TM.getInstrInfo().isReturn(Opcode)) {
AddedInstrns *AI = AddedInstrMap[ MInst]; AddedInstrns *AI = AddedInstrMap[ MInst];
if ( !AI ) { if ( !AI ) {
@ -469,12 +454,10 @@ void PhyRegAlloc::updateMachineCode()
// //
mcInfo.popAllTempValues(TM); mcInfo.popAllTempValues(TM);
if( (TM.getInstrInfo()).isCall( Opcode ) ) if (TM.getInstrInfo().isCall(Opcode))
MRI.colorCallArgs( MInst, LRI, AI, *this, *BBI ); MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
else if (TM.getInstrInfo().isReturn(Opcode))
else if ( (TM.getInstrInfo()).isReturn(Opcode) ) MRI.colorRetValue(MInst, LRI, AI);
MRI.colorRetValue( MInst, LRI, AI );
} }
@ -586,8 +569,8 @@ void PhyRegAlloc::updateMachineCode()
// If there are instructions to be added *after* this machine // If there are instructions to be added *after* this machine
// instruction, add them now // instruction, add them now
// //
if( AddedInstrMap[ MInst ] && if(AddedInstrMap[MInst] &&
! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) { !AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
// if there are delay slots for this instruction, the instructions // if there are delay slots for this instruction, the instructions
// added after it must really go after the delayed instruction(s) // added after it must really go after the delayed instruction(s)
@ -595,7 +578,7 @@ void PhyRegAlloc::updateMachineCode()
// corresponding delayed instruction // corresponding delayed instruction
unsigned delay; unsigned delay;
if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){ if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
move2DelayedInstr(MInst, *(MInstIterator+delay) ); move2DelayedInstr(MInst, *(MInstIterator+delay) );
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot"; if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
@ -689,13 +672,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
// actual loading instruction // actual loading instruction
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType); AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
if( MIBef ) if(MIBef)
(AI->InstrnsBefore).push_back(MIBef); AI->InstrnsBefore.push_back(MIBef);
(AI->InstrnsBefore).push_back(AdIMid); AI->InstrnsBefore.push_back(AdIMid);
if( MIAft) if(MIAft)
(AI->InstrnsAfter).push_front(MIAft); AI->InstrnsAfter.push_front(MIAft);
} }
@ -707,13 +690,13 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
// actual storing instruction // actual storing instruction
AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType); AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
if( MIBef ) if (MIBef)
(AI->InstrnsBefore).push_back(MIBef); AI->InstrnsBefore.push_back(MIBef);
(AI->InstrnsAfter).push_front(AdIMid); AI->InstrnsAfter.push_front(AdIMid);
if( MIAft) if (MIAft)
(AI->InstrnsAfter).push_front(MIAft); AI->InstrnsAfter.push_front(MIAft);
} // if !DEF } // if !DEF
@ -1080,16 +1063,13 @@ void PhyRegAlloc::colorCallRetArgs()
if( (TM.getInstrInfo()).isCall( OpCode ) ) if (TM.getInstrInfo().isCall(OpCode))
MRI.colorCallArgs( CRMI, LRI, AI, *this ); MRI.colorCallArgs(CRMI, LRI, AI, *this);
else if (TM.getInstrInfo().isReturn(OpCode))
else if ( (TM.getInstrInfo()).isReturn(OpCode) )
MRI.colorRetValue( CRMI, LRI, AI ); MRI.colorRetValue( CRMI, LRI, AI );
else
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" ); assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
} }
} }
#endif #endif
@ -1100,16 +1080,14 @@ void PhyRegAlloc::colorCallRetArgs()
void PhyRegAlloc::colorIncomingArgs() void PhyRegAlloc::colorIncomingArgs()
{ {
const BasicBlock *const FirstBB = Meth->front(); const BasicBlock *const FirstBB = Meth->front();
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin()); const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
assert( FirstMI && "No machine instruction in entry BB"); assert(FirstMI && "No machine instruction in entry BB");
AddedInstrns *AI = AddedInstrMap[ FirstMI ]; AddedInstrns *AI = AddedInstrMap[FirstMI];
if (!AI) { if (!AI)
AI = new AddedInstrns(); AddedInstrMap[FirstMI] = AI = new AddedInstrns();
AddedInstrMap[FirstMI] = AI;
}
MRI.colorMethodArgs(Meth, LRI, AI ); MRI.colorMethodArgs(Meth, LRI, AI);
} }
@ -1139,16 +1117,12 @@ void PhyRegAlloc::markUnusableSugColors()
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end(); LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
for( ; HMI != HMIEnd ; ++HMI ) { for(; HMI != HMIEnd ; ++HMI ) {
if (HMI->first) {
if( (*HMI).first ) { LiveRange *L = HMI->second; // get the LiveRange
if (L) {
LiveRange *L = (*HMI).second; // get the LiveRange if(L->hasSuggestedColor()) {
int RCID = L->getRegClass()->getID();
if(L) {
if( L->hasSuggestedColor() ) {
int RCID = (L->getRegClass())->getID();
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) && if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
L->isCallInterference() ) L->isCallInterference() )
L->setSuggestedColorUsable( false ); L->setSuggestedColorUsable( false );
@ -1202,7 +1176,7 @@ void PhyRegAlloc::allocateRegisters()
// //
LRI.constructLiveRanges(); // create LR info LRI.constructLiveRanges(); // create LR info
if( DEBUG_RA ) if (DEBUG_RA)
LRI.printLiveRanges(); LRI.printLiveRanges();
createIGNodeListsAndIGs(); // create IGNode list and IGs createIGNodeListsAndIGs(); // create IGNode list and IGs
@ -1210,7 +1184,7 @@ void PhyRegAlloc::allocateRegisters()
buildInterferenceGraphs(); // build IGs in all reg classes buildInterferenceGraphs(); // build IGs in all reg classes
if( DEBUG_RA ) { if (DEBUG_RA) {
// print all LRs in all reg classes // print all LRs in all reg classes
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++) for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[ rc ]->printIGNodeList(); RegClassList[ rc ]->printIGNodeList();
@ -1257,19 +1231,16 @@ void PhyRegAlloc::allocateRegisters()
// //
colorIncomingArgs(); colorIncomingArgs();
// Now update the machine code with register names and add any // Now update the machine code with register names and add any
// additional code inserted by the register allocator to the instruction // additional code inserted by the register allocator to the instruction
// stream // stream
// //
updateMachineCode(); updateMachineCode();
if (DEBUG_RA) { if (DEBUG_RA) {
MachineCodeForMethod::get(Meth).dump(); MachineCodeForMethod::get(Meth).dump();
printMachineCode(); // only for DEBUGGING printMachineCode(); // only for DEBUGGING
} }
} }