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ARM: provide VFP aliases for pre-V6 mnemonics
In order to provide compatibility with the GNU assembler, provide aliases for pre-UAL mnemonics for floating point operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool
parent
a4f62f85a2
commit
dd2836776f
@ -207,6 +207,27 @@ defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
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def : MnemonicAlias<"vldm", "vldmia">;
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def : MnemonicAlias<"vstm", "vstmia">;
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// FLDM/FSTM - Load / Store multiple single / double precision registers for
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// pre-ARMv6 cores.
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// These instructions are deprecated!
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def : VFP2MnemonicAlias<"fldmias", "vldmia">;
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def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
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def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
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def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
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def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
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def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
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def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
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def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
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def : VFP2MnemonicAlias<"fstmias", "vstmia">;
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def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
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def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
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def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
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def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
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def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
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def : VFP2MnemonicAlias<"fstmead", "vstmia">;
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def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
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def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
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Requires<[HasVFP2]>;
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def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
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@ -247,7 +268,7 @@ multiclass vfp_ldstx_mult<string asm, bit L_bit> {
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AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
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IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 1;
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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}
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@ -255,6 +276,12 @@ multiclass vfp_ldstx_mult<string asm, bit L_bit> {
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defm FLDM : vfp_ldstx_mult<"fldm", 1>;
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defm FSTM : vfp_ldstx_mult<"fstm", 0>;
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def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
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def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
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def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
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def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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//
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@ -5111,6 +5111,15 @@ static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
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bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// FIXME: Can this be done via tablegen in some fashion?
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bool HasPrecisionRestrictions;
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bool AcceptDoublePrecisionOnly;
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bool AcceptSinglePrecisionOnly;
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HasPrecisionRestrictions = Name.startswith("fldm") || Name.startswith("fstm");
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AcceptDoublePrecisionOnly =
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HasPrecisionRestrictions && (Name.back() == 'd' || Name.back() == 'x');
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AcceptSinglePrecisionOnly = HasPrecisionRestrictions && Name.back() == 's';
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// Apply mnemonic aliases before doing anything else, as the destination
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// mnemonic may include suffices and we want to handle them normally.
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// The generic tblgen'erated code does this later, at the start of
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@ -5279,6 +5288,26 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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Parser.Lex(); // Consume the EndOfStatement
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if (HasPrecisionRestrictions) {
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ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
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assert(Op->isRegList());
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const SmallVectorImpl<unsigned> &RegList = Op->getRegList();
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for (SmallVectorImpl<unsigned>::const_iterator RLI = RegList.begin(),
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RLE = RegList.end();
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RLI != RLE; ++RLI) {
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if (AcceptSinglePrecisionOnly &&
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!ARMMCRegisterClasses[ARM::SPRRegClassID].contains(*RLI))
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return Error(Op->getStartLoc(),
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"VFP/Neon single precision register expected");
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else if (AcceptDoublePrecisionOnly &&
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!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(*RLI))
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return Error(Op->getStartLoc(),
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"VFP/Neon double precision register expected");
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else
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llvm_unreachable("must have single or double precision restrictions");
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}
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}
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// Some instructions, mostly Thumb, have forms for the same mnemonic that
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// do and don't have a cc_out optional-def operand. With some spot-checks
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// of the operand list, we can figure out which variant we're trying to
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97
test/MC/ARM/vfp-aliases-diagnostics.s
Normal file
97
test/MC/ARM/vfp-aliases-diagnostics.s
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@ -0,0 +1,97 @@
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@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 \
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@ RUN: | FileCheck %s
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.syntax unified
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.fpu vfp
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.type aliases,%function
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aliases:
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fstmfdd sp!, {s0}
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fstmead sp!, {s0}
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fstmdbd sp!, {s0}
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fstmiad sp!, {s0}
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fstmfds sp!, {d0}
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fstmeas sp!, {d0}
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fstmdbs sp!, {d0}
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fstmias sp!, {d0}
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fldmias sp!, {d0}
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fldmdbs sp!, {d0}
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fldmeas sp!, {d0}
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fldmfds sp!, {d0}
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fldmiad sp!, {s0}
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fldmdbd sp!, {s0}
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fldmead sp!, {s0}
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fldmfdd sp!, {s0}
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fstmeax sp!, {s0}
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fldmfdx sp!, {s0}
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fstmfdx sp!, {s0}
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fldmeax sp!, {s0}
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@ CHECK-LABEL: aliases
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmfdd sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmead sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmdbd sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmiad sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fstmfds sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fstmeas sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fstmdbs sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fstmias sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fldmias sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fldmdbs sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fldmeas sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon single precision register expected
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@ CHECK: fldmfds sp!, {d0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmiad sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmdbd sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmead sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmfdd sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmeax sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmfdx sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fstmfdx sp!, {s0}
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@ CHECK: ^
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@ CHECK: error: VFP/Neon double precision register expected
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@ CHECK: fldmeax sp!, {s0}
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@ CHECK: ^
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53
test/MC/ARM/vfp-aliases.s
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53
test/MC/ARM/vfp-aliases.s
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@ -0,0 +1,53 @@
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@ RUN: llvm-mc -triple armv7-eabi -filetype asm -o - %s | FileCheck %s
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.syntax unified
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.fpu vfp
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.type aliases,%function
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aliases:
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fstmfdd sp!, {d0}
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fstmead sp!, {d0}
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fstmdbd sp!, {d0}
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fstmiad sp!, {d0}
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fstmfds sp!, {s0}
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fstmeas sp!, {s0}
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fstmdbs sp!, {s0}
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fstmias sp!, {s0}
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fldmias sp!, {s0}
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fldmdbs sp!, {s0}
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fldmeas sp!, {s0}
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fldmfds sp!, {s0}
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fldmiad sp!, {d0}
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fldmdbd sp!, {d0}
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fldmead sp!, {d0}
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fldmfdd sp!, {d0}
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fstmeax sp!, {d0}
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fldmfdx sp!, {d0}
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fstmfdx sp!, {d0}
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fldmeax sp!, {d0}
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@ CHECK-LABEL: aliases
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@ CHECK: vpush {d0}
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@ CHECK: vstmia sp!, {d0}
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@ CHECK: vpush {d0}
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@ CHECK: vstmia sp!, {d0}
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@ CHECK: vpush {s0}
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@ CHECK: vstmia sp!, {s0}
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@ CHECK: vpush {s0}
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@ CHECK: vstmia sp!, {s0}
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@ CHECK: vpop {s0}
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@ CHECK: vldmdb sp!, {s0}
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@ CHECK: vldmdb sp!, {s0}
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@ CHECK: vpop {s0}
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@ CHECK: vpop {d0}
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@ CHECK: vldmdb sp!, {d0}
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@ CHECK: vldmdb sp!, {d0}
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@ CHECK: vpop {d0}
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@ CHECK: fstmiax sp!, {d0}
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@ CHECK: fldmiax sp!, {d0}
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@ CHECK: fstmdbx sp!, {d0}
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@ CHECK: fldmdbx sp!, {d0}
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