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Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121584 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,6 +36,10 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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if (Hint && TargetRegisterInfo::isVirtualRegister(Hint))
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if (Hint && TargetRegisterInfo::isVirtualRegister(Hint))
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Hint = VRM.getPhys(Hint);
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Hint = VRM.getPhys(Hint);
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// The remaining allocation order may depend on the hint.
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tie(Begin, End) = VRM.getTargetRegInfo()
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.getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
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// Target-dependent hints require resolution.
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// Target-dependent hints require resolution.
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if (HintPair.first)
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if (HintPair.first)
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Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint,
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Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint,
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@ -45,10 +49,6 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
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if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
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!RC->contains(Hint) || ReservedRegs.test(Hint)))
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!RC->contains(Hint) || ReservedRegs.test(Hint)))
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Hint = 0;
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Hint = 0;
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// The remaining allocation order may also depend on the hint.
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tie(Begin, End) = VRM.getTargetRegInfo()
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.getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
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}
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}
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unsigned AllocationOrder::next() {
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unsigned AllocationOrder::next() {
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#define DEBUG_TYPE "regalloc"
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#include "AllocationOrder.h"
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#include "LiveIntervalUnion.h"
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "Spiller.h"
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@ -175,12 +176,9 @@ bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
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assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
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assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
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"inconsistent phys reg assigment");
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"inconsistent phys reg assigment");
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const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg);
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AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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while (unsigned PhysReg = Order.next()) {
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E = TRC->allocation_order_end(*MF);
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if (PhysReg == OldPhysReg)
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I != E; ++I) {
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unsigned PhysReg = *I;
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if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
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continue;
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continue;
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if (checkUncachedInterference(InterferingVReg, PhysReg))
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if (checkUncachedInterference(InterferingVReg, PhysReg))
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@ -235,21 +233,8 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
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DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
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// Preferred physical register computed from hints.
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AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
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unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
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while (unsigned PhysReg = Order.next()) {
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// Try a hinted allocation.
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if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
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checkPhysRegInterference(VirtReg, Hint) == 0)
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return Hint;
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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I != E; ++I) {
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unsigned PhysReg = *I;
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if (ReservedRegs.test(PhysReg)) continue;
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// Check interference and as a side effect, intialize queries for this
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// Check interference and as a side effect, intialize queries for this
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// VirtReg and its aliases.
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// VirtReg and its aliases.
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unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);
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unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);
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