6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-11 21:38:19 +00:00
Code Issues Projects Releases Wiki Activity

Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121584 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-12-10 22:21:05 +00:00
parent 746fa17d59
commit dd479e9769
2 changed files with 10 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/AllocationOrder.cpp
View File

@ -36,6 +36,10 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
if (Hint && TargetRegisterInfo::isVirtualRegister(Hint)) if (Hint && TargetRegisterInfo::isVirtualRegister(Hint))
Hint = VRM.getPhys(Hint); Hint = VRM.getPhys(Hint);
// The remaining allocation order may depend on the hint.
tie(Begin, End) = VRM.getTargetRegInfo()
.getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
// Target-dependent hints require resolution. // Target-dependent hints require resolution.
if (HintPair.first) if (HintPair.first)
Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint, Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint,
@ -45,10 +49,6 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
!RC->contains(Hint) || ReservedRegs.test(Hint))) !RC->contains(Hint) || ReservedRegs.test(Hint)))
Hint = 0; Hint = 0;
// The remaining allocation order may also depend on the hint.
tie(Begin, End) = VRM.getTargetRegInfo()
.getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
} }
unsigned AllocationOrder::next() { unsigned AllocationOrder::next() {

27
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regalloc" #define DEBUG_TYPE "regalloc"
#include "AllocationOrder.h"
#include "LiveIntervalUnion.h" #include "LiveIntervalUnion.h"
#include "RegAllocBase.h" #include "RegAllocBase.h"
#include "Spiller.h" #include "Spiller.h"
@ -175,12 +176,9 @@ bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) && assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
"inconsistent phys reg assigment"); "inconsistent phys reg assigment");
const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg); AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF), while (unsigned PhysReg = Order.next()) {
E = TRC->allocation_order_end(*MF); if (PhysReg == OldPhysReg)
I != E; ++I) {
unsigned PhysReg = *I;
if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
continue; continue;
if (checkUncachedInterference(InterferingVReg, PhysReg)) if (checkUncachedInterference(InterferingVReg, PhysReg))
@ -235,21 +233,8 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg); const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' '); DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
// Preferred physical register computed from hints. AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
unsigned Hint = VRM->getRegAllocPref(VirtReg.reg); while (unsigned PhysReg = Order.next()) {
// Try a hinted allocation.
if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
checkPhysRegInterference(VirtReg, Hint) == 0)
return Hint;
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
E = TRC->allocation_order_end(*MF);
I != E; ++I) {
unsigned PhysReg = *I;
if (ReservedRegs.test(PhysReg)) continue;
// Check interference and as a side effect, intialize queries for this // Check interference and as a side effect, intialize queries for this
// VirtReg and its aliases. // VirtReg and its aliases.
unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg); unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);