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ARM parsing datatype suffix variants for non-writeback VST1 instructions.

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rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-14 23:43:46 +00:00
parent e052b9afa1
commit dd47e0b5d4
2 changed files with 65 additions and 0 deletions
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44
lib/Target/ARM/ARMInstrNEON.td
View File

@ -5239,3 +5239,47 @@ defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
(VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
(VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
// VST1 requires a size suffix, but also accepts type specific variants.
// Load one D register.
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d16 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
// Load two D registers.
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1q16 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
(VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
// FIXME: The three and four register VST1 instructions haven't been moved
// to the VecList* encoding yet, so we can't do assembly parsing support
// for them. Uncomment these when that happens.
// Load three D registers.
//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
// Load four D registers.
//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
// (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;

21
test/MC/ARM/neon-vst-encoding.s
View File

@ -111,3 +111,24 @@
@ FIXME: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4]
@ FIXME: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4]
@ FIXME: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4]
@ Spot-check additional size-suffix aliases.
vst1.8 {d2}, [r2]
vst1.p8 {d2}, [r2]
vst1.u8 {d2}, [r2]
vst1.8 {q2}, [r2]
vst1.p8 {q2}, [r2]
vst1.u8 {q2}, [r2]
vst1.f32 {q2}, [r2]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]