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Rename TRI::getAllocationOrder() to getRawAllocationOrder().

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Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-16 23:31:16 +00:00
parent c02a6fa7d8
commit dd5a847152
5 changed files with 51 additions and 67 deletions
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14
lib/CodeGen/RegAllocLinearScan.cpp
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@ -1440,13 +1440,13 @@ unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
if (TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
physReg = vrm_->getPhys(physReg);
TargetRegisterClass::iterator I, E;
tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
assert(I != E && "No allocatable register in this register class!");
ArrayRef<unsigned> Order = tri_->getRawAllocationOrder(RC, Hint.first,
physReg, *mf_);
assert(!Order.empty() && "No allocatable register in this register class!");
// Scan for the first available register.
for (; I != E; ++I) {
unsigned Reg = *I;
for (unsigned i = 0; i != Order.size(); ++i) {
unsigned Reg = Order[i];
// Ignore "downgraded" registers.
if (SkipDGRegs && DowngradedRegs.count(Reg))
continue;
@ -1476,8 +1476,8 @@ unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
// inactive count. Alkis found that this reduced register pressure very
// slightly on X86 (in rev 1.94 of this file), though this should probably be
// reevaluated now.
for (; I != E; ++I) {
unsigned Reg = *I;
for (unsigned i = 0; i != Order.size(); ++i) {
unsigned Reg = Order[i];
// Ignore "downgraded" registers.
if (SkipDGRegs && DowngradedRegs.count(Reg))
continue;