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https://github.com/c64scene-ar/llvm-6502.git
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FastISel support for exception-handling constructs.
- Move the EH landing-pad code and adjust it so that it works with FastISel as well as with SDISel. - Add FastISel support for @llvm.eh.exception and @llvm.eh.selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,12 +16,14 @@
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#include "llvm/BasicBlock.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class AllocaInst;
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class ConstantFP;
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class Instruction;
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class MachineBasicBlock;
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class MachineConstantPool;
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class MachineFunction;
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@ -44,6 +46,9 @@ protected:
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DenseMap<const Value *, unsigned> &ValueMap;
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
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DenseMap<const AllocaInst *, int> &StaticAllocaMap;
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#ifndef NDEBUG
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SmallSet<Instruction*, 8> &CatchInfoLost;
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#endif
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MachineFunction &MF;
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MachineModuleInfo *MMI;
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MachineRegisterInfo &MRI;
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@ -108,7 +113,11 @@ protected:
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am);
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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);
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/// FastEmit_r - This method is called by target-independent code
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/// to request that an instruction with the given type and opcode
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@ -30,6 +30,7 @@ namespace llvm {
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class MachineInstr;
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class MachineModuleInfo;
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class TargetLowering;
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class TargetInstrInfo;
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class FunctionLoweringInfo;
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class HazardRecognizer;
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class GCFunctionInfo;
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@ -107,7 +108,8 @@ protected:
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private:
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void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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MachineModuleInfo *MMI);
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MachineModuleInfo *MMI,
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const TargetInstrInfo &TII);
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void FinishBasicBlock();
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void SelectBasicBlock(BasicBlock *LLVMBB,
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@ -28,6 +28,7 @@
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#include "llvm/CodeGen/RuntimeLibcalls.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include <map>
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#include <vector>
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@ -1124,7 +1125,11 @@ public:
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MachineModuleInfo *,
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DenseMap<const Value *, unsigned> &,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &,
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DenseMap<const AllocaInst *, int> &) {
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DenseMap<const AllocaInst *, int> &
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &CatchInfoLost
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#endif
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) {
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return 0;
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}
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@ -51,6 +51,7 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "SelectionDAGBuild.h"
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using namespace llvm;
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unsigned FastISel::getRegForValue(Value *V) {
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@ -379,6 +380,66 @@ bool FastISel::SelectCall(User *I) {
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}
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return true;
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}
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case Intrinsic::eh_exception: {
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MVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
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default: break;
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case TargetLowering::Expand: {
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if (!MBB->isLandingPad()) {
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// FIXME: Mark exception register as live in. Hack for PR1508.
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unsigned Reg = TLI.getExceptionAddressRegister();
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if (Reg) MBB->addLiveIn(Reg);
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}
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unsigned Reg = TLI.getExceptionAddressRegister();
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Reg, RC, RC);
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assert(InsertedCopy && "Can't copy address registers!");
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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break;
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}
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case Intrinsic::eh_selector_i32:
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case Intrinsic::eh_selector_i64: {
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MVT VT = TLI.getValueType(I->getType());
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switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
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default: break;
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case TargetLowering::Expand: {
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MVT VT = (IID == Intrinsic::eh_selector_i32 ?
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MVT::i32 : MVT::i64);
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if (MMI) {
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if (MBB->isLandingPad())
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AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
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else {
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#ifndef NDEBUG
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CatchInfoLost.insert(cast<CallInst>(I));
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#endif
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// FIXME: Mark exception selector register as live in. Hack for PR1508.
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unsigned Reg = TLI.getExceptionSelectorRegister();
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if (Reg) MBB->addLiveIn(Reg);
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}
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unsigned Reg = TLI.getExceptionSelectorRegister();
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
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Reg, RC, RC);
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assert(InsertedCopy && "Can't copy address registers!");
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UpdateValueMap(I, ResultReg);
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} else {
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unsigned ResultReg =
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getRegForValue(Constant::getNullValue(I->getType()));
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UpdateValueMap(I, ResultReg);
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}
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return true;
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}
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}
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break;
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}
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}
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return false;
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}
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@ -607,11 +668,18 @@ FastISel::FastISel(MachineFunction &mf,
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am)
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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)
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: MBB(0),
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ValueMap(vm),
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MBBMap(bm),
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StaticAllocaMap(am),
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#ifndef NDEBUG
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CatchInfoLost(cil),
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#endif
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MF(mf),
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MMI(mmi),
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MRI(MF.getRegInfo()),
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@ -314,7 +314,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
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// Mark landing pad.
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FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
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SelectAllBasicBlocks(Fn, MF, MMI);
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SelectAllBasicBlocks(Fn, MF, MMI, TII);
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// If the first basic block in the function has live ins that need to be
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// copied into vregs, emit the copies into the top of the block before
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@ -452,48 +452,6 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
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BasicBlock::iterator End) {
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SDL->setCurrentBasicBlock(BB);
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MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
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if (MMI && BB->isLandingPad()) {
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// Add a label to mark the beginning of the landing pad. Deletion of the
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// landing pad can thus be detected via the MachineModuleInfo.
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unsigned LabelID = MMI->addLandingPad(BB);
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CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL,
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CurDAG->getEntryNode(), LabelID));
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// Mark exception register as live in.
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unsigned Reg = TLI.getExceptionAddressRegister();
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if (Reg) BB->addLiveIn(Reg);
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// Mark exception selector register as live in.
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Reg = TLI.getExceptionSelectorRegister();
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if (Reg) BB->addLiveIn(Reg);
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// FIXME: Hack around an exception handling flaw (PR1508): the personality
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// function and list of typeids logically belong to the invoke (or, if you
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// like, the basic block containing the invoke), and need to be associated
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// with it in the dwarf exception handling tables. Currently however the
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// information is provided by an intrinsic (eh.selector) that can be moved
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// to unexpected places by the optimizers: if the unwind edge is critical,
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// then breaking it can result in the intrinsics being in the successor of
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// the landing pad, not the landing pad itself. This results in exceptions
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// not being caught because no typeids are associated with the invoke.
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// This may not be the only way things can go wrong, but it is the only way
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// we try to work around for the moment.
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BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
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if (Br && Br->isUnconditional()) { // Critical edge?
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BasicBlock::iterator I, E;
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for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
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if (isa<EHSelectorInst>(I))
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break;
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if (I == E)
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// No catch info found - try to extract some from the successor.
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copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
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}
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}
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// Lower all of the non-terminator instructions.
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for (BasicBlock::iterator I = Begin; I != End; ++I)
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if (!isa<TerminatorInst>(I))
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@ -708,14 +666,19 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
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}
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void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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MachineModuleInfo *MMI) {
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MachineModuleInfo *MMI,
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const TargetInstrInfo &TII) {
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// Initialize the Fast-ISel state, if needed.
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FastISel *FastIS = 0;
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if (EnableFastISel)
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FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
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FuncInfo->ValueMap,
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FuncInfo->MBBMap,
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FuncInfo->StaticAllocaMap);
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FuncInfo->StaticAllocaMap
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#ifndef NDEBUG
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, FuncInfo->CatchInfoLost
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#endif
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);
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// Iterate over all basic blocks in the function.
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for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
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@ -746,9 +709,49 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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}
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}
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if (MMI && BB->isLandingPad()) {
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// Add a label to mark the beginning of the landing pad. Deletion of the
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// landing pad can thus be detected via the MachineModuleInfo.
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unsigned LabelID = MMI->addLandingPad(BB);
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const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
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BuildMI(BB, II).addImm(LabelID);
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// Mark exception register as live in.
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unsigned Reg = TLI.getExceptionAddressRegister();
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if (Reg) BB->addLiveIn(Reg);
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// Mark exception selector register as live in.
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Reg = TLI.getExceptionSelectorRegister();
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if (Reg) BB->addLiveIn(Reg);
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// FIXME: Hack around an exception handling flaw (PR1508): the personality
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// function and list of typeids logically belong to the invoke (or, if you
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// like, the basic block containing the invoke), and need to be associated
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// with it in the dwarf exception handling tables. Currently however the
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// information is provided by an intrinsic (eh.selector) that can be moved
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// to unexpected places by the optimizers: if the unwind edge is critical,
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// then breaking it can result in the intrinsics being in the successor of
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// the landing pad, not the landing pad itself. This results in exceptions
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// not being caught because no typeids are associated with the invoke.
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// This may not be the only way things can go wrong, but it is the only way
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// we try to work around for the moment.
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BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
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if (Br && Br->isUnconditional()) { // Critical edge?
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BasicBlock::iterator I, E;
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for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
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if (isa<EHSelectorInst>(I))
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break;
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if (I == E)
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// No catch info found - try to extract some from the successor.
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copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
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}
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}
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// Before doing SelectionDAG ISel, see if FastISel has been requested.
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// FastISel doesn't support EH landing pads, which require special handling.
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if (FastIS && !SuppressFastISel && !BB->isLandingPad()) {
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if (FastIS && !SuppressFastISel) {
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// Emit code for any incoming arguments. This must happen before
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// beginning FastISel on the entry block.
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if (LLVMBB == &Fn.getEntryBlock()) {
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am)
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: FastISel(mf, mmi, vm, bm, am) {
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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)
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: FastISel(mf, mmi, vm, bm, am
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#ifndef NDEBUG
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, cil
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#endif
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) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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X86ScalarSSEf64 = Subtarget->hasSSE2();
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@ -1391,7 +1399,15 @@ namespace llvm {
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am) {
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return new X86FastISel(mf, mmi, vm, bm, am);
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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) {
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return new X86FastISel(mf, mmi, vm, bm, am
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#ifndef NDEBUG
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, cil
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#endif
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);
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}
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}
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *,
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MachineBasicBlock *> &bm,
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DenseMap<const AllocaInst *, int> &am) {
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return X86::createFastISel(mf, mmo, vm, bm, am);
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DenseMap<const AllocaInst *, int> &am
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &cil
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#endif
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) {
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return X86::createFastISel(mf, mmo, vm, bm, am
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#ifndef NDEBUG
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, cil
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#endif
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);
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}
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@ -493,7 +493,11 @@ namespace llvm {
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &,
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DenseMap<const AllocaInst *, int> &);
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DenseMap<const AllocaInst *, int> &
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &
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#endif
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);
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private:
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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@ -638,7 +642,11 @@ namespace llvm {
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MachineModuleInfo *mmi,
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DenseMap<const Value *, unsigned> &,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &,
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DenseMap<const AllocaInst *, int> &);
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DenseMap<const AllocaInst *, int> &
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#ifndef NDEBUG
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, SmallSet<Instruction*, 8> &
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#endif
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);
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}
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}
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