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AArch64: enable Cortex-A57 FP balancing on Cortex-A53.

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Benchmarks have shown that it's harmless to the performance there, and having a
unified set of passes between the two cores where possible helps big.LITTLE
deployment.

Patch by Z. Zheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2014-10-28 01:24:32 +00:00
parent c35c39b73c
commit dd778c6c9f
2 changed files with 12 additions and 5 deletions
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3
lib/Target/AArch64/AArch64TargetMachine.cpp
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@@ -251,7 +251,8 @@ bool AArch64PassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination) if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions()); addPass(createAArch64DeadRegisterDefinitions());
if (TM->getOptLevel() != CodeGenOpt::None && if (TM->getOptLevel() != CodeGenOpt::None &&
TM->getSubtarget<AArch64Subtarget>().isCortexA57() && (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
usingDefaultRegAlloc()) usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57. // Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing()); addPass(createAArch64A57FPLoadBalancing());

14
test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
View File

@@ -1,5 +1,7 @@
; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN ; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-EVEN
; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD ; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-ODD
; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN
; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD
; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so ; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so
; our test strategy is to: ; our test strategy is to:
@@ -73,7 +75,9 @@ entry:
; CHECK: fmsub [[x]] ; CHECK: fmsub [[x]]
; CHECK: fmadd [[y]] ; CHECK: fmadd [[y]]
; CHECK: fmadd [[x]] ; CHECK: fmadd [[x]]
; CHECK: stp [[x]], [[y]] ; CHECK-A57: stp [[x]], [[y]]
; CHECK-A53-DAG: str [[x]]
; CHECK-A53-DAG: str [[y]]
define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 { define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 {
entry: entry:
@@ -166,7 +170,9 @@ declare void @g(...) #1
; CHECK: fmsub [[x]] ; CHECK: fmsub [[x]]
; CHECK: fmadd [[y]] ; CHECK: fmadd [[y]]
; CHECK: fmadd [[x]] ; CHECK: fmadd [[x]]
; CHECK: stp [[x]], [[y]] ; CHECK-A57: stp [[x]], [[y]]
; CHECK-A53-DAG: str [[x]]
; CHECK-A53-DAG: str [[y]]
define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 { define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 {
entry: entry: