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Add instruction encodings / disassembly support for 0r instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2012-12-17 12:26:29 +00:00
parent 2694948966
commit dd78daa199
3 changed files with 32 additions and 9 deletions
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5
lib/Target/XCore/XCoreInstrFormats.td
View File

@ -95,8 +95,11 @@ class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{3-0} = a; let Inst{3-0} = a;
} }
class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern> class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> { : InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc{9-5};
let Inst{10-5} = 0b111111;
let Inst{4-0} = opc{4-0};
} }
class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern> class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>

16
lib/Target/XCore/XCoreInstrInfo.td
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@ -1018,31 +1018,31 @@ def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
// stet, getkep, getksp, setkep, getid, kret, dcall, dret, // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
// dentsp, drestsp // dentsp, drestsp
def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
let Defs = [R11] in { let Defs = [R11] in {
def GETID_0R : _F0R<(outs), (ins), def GETID_0R : _F0R<0b0001001110, (outs), (ins),
"get r11, id", "get r11, id",
[(set R11, (int_xcore_getid))]>; [(set R11, (int_xcore_getid))]>;
def GETED_0R : _F0R<(outs), (ins), def GETED_0R : _F0R<0b0000111110, (outs), (ins),
"get r11, ed", "get r11, ed",
[(set R11, (int_xcore_geted))]>; [(set R11, (int_xcore_geted))]>;
def GETET_0R : _F0R<(outs), (ins), def GETET_0R : _F0R<0b0000111111, (outs), (ins),
"get r11, et", "get r11, et",
[(set R11, (int_xcore_getet))]>; [(set R11, (int_xcore_getet))]>;
} }
def SSYNC_0r : _F0R<(outs), (ins), def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
"ssync", "ssync",
[(int_xcore_ssync)]>; [(int_xcore_ssync)]>;
let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
hasSideEffects = 1 in hasSideEffects = 1 in
def WAITEU_0R : _F0R<(outs), (ins), def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
"waiteu", "waiteu",
[(brind (int_xcore_waitevent))]>; [(brind (int_xcore_waitevent))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Non-Instruction Patterns // Non-Instruction Patterns

20
test/MC/Disassembler/XCore/xcore.txt
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@ -1,6 +1,26 @@
# RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s
# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: .section __TEXT,__text,regular,pure_instructions
# 0r instructions
# CHECK: clre
0xed 0x07
# CHECK: get r11, id
0xee 0x17
# CHECK: get r11, ed
0xfe 0x0f
# CHECK: get r11, et
0xff 0x0f
# CHECK: ssync
0xee 0x07
# CHECK: waiteu
0xec 0x07
# 1r instructions # 1r instructions
# CHECK: msync res[r0] # CHECK: msync res[r0]