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Add instruction encodings / disassembly support for 0r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -95,8 +95,11 @@ class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{3-0} = a;
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}
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class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{9-5};
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let Inst{10-5} = 0b111111;
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let Inst{4-0} = opc{4-0};
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}
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class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -1018,29 +1018,29 @@ def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
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// stet, getkep, getksp, setkep, getid, kret, dcall, dret,
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// dentsp, drestsp
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def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>;
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def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
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let Defs = [R11] in {
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def GETID_0R : _F0R<(outs), (ins),
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def GETID_0R : _F0R<0b0001001110, (outs), (ins),
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"get r11, id",
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[(set R11, (int_xcore_getid))]>;
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def GETED_0R : _F0R<(outs), (ins),
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def GETED_0R : _F0R<0b0000111110, (outs), (ins),
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"get r11, ed",
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[(set R11, (int_xcore_geted))]>;
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def GETET_0R : _F0R<(outs), (ins),
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def GETET_0R : _F0R<0b0000111111, (outs), (ins),
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"get r11, et",
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[(set R11, (int_xcore_getet))]>;
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}
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def SSYNC_0r : _F0R<(outs), (ins),
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def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
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"ssync",
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[(int_xcore_ssync)]>;
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let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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hasSideEffects = 1 in
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def WAITEU_0R : _F0R<(outs), (ins),
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def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
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"waiteu",
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[(brind (int_xcore_waitevent))]>;
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@ -1,6 +1,26 @@
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# RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s
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# CHECK: .section __TEXT,__text,regular,pure_instructions
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# 0r instructions
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# CHECK: clre
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0xed 0x07
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# CHECK: get r11, id
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0xee 0x17
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# CHECK: get r11, ed
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0xfe 0x0f
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# CHECK: get r11, et
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0xff 0x0f
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# CHECK: ssync
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0xee 0x07
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# CHECK: waiteu
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0xec 0x07
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# 1r instructions
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# CHECK: msync res[r0]
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