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Avoid -Wunused-variable in -asserts builds

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Beaumont-Gay
2011-03-22 00:37:28 +00:00
parent e17232ee4d
commit ddb657c63d
1 changed files with 4 additions and 6 deletions
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10
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@@ -607,11 +607,6 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
const TargetOperandInfo *OpInfo = TID.OpInfo; const TargetOperandInfo *OpInfo = TID.OpInfo;
unsigned &OpIdx = NumOpsAdded; unsigned &OpIdx = NumOpsAdded;
// Table A6-5 16-bit Thumb Load/store instructions
// opA = 0b0101 for STR/LDR (register) and friends.
// Otherwise, we have STR/LDR (immediate) and friends.
bool Imm5 = (opA != 5);
assert(NumOps >= 2 assert(NumOps >= 2
&& OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[0].RegClass == ARM::tGPRRegClassID
&& OpInfo[1].RegClass == ARM::tGPRRegClassID && OpInfo[1].RegClass == ARM::tGPRRegClassID
@@ -632,7 +627,10 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
!OpInfo[OpIdx].isOptionalDef()) { !OpInfo[OpIdx].isOptionalDef()) {
assert(Imm5 && "Immediate operand expected for this opcode"); // Table A6-5 16-bit Thumb Load/store instructions
// opA = 0b0101 for STR/LDR (register) and friends.
// Otherwise, we have STR/LDR (immediate) and friends.
assert(opA != 5 && "Immediate operand expected for this opcode");
MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn))); MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
++OpIdx; ++OpIdx;
} else { } else {