mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
1f4abcfa5c
commit
ddc918b379
@ -1803,6 +1803,16 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
|
||||
}
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1, isCodeGenOnly = 1 in {
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
||||
defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
|
||||
|
||||
} // neverHasSideEffects
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
||||
isCodeGenOnly = 1 in {
|
||||
def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
||||
|
@ -549,6 +549,20 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
|
||||
T1Encoding<T1Enc>;
|
||||
}
|
||||
|
||||
/* FIXME: Uncommented, this causes a decoding conflict.
|
||||
let neverHasSideEffects = 1 in {
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
||||
defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
|
||||
{1,1,0,0,1,?}, 1>;
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
|
||||
{1,1,0,0,0,?}, 0>;
|
||||
|
||||
} // neverHasSideEffects
|
||||
*/
|
||||
|
||||
// These require base address to be written back or one of the loaded regs.
|
||||
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
||||
isCodeGenOnly = 1 in {
|
||||
|
@ -1347,6 +1347,16 @@ multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
|
||||
}
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1, isCodeGenOnly = 1 in {
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
||||
defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
|
||||
|
||||
} // neverHasSideEffects
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
||||
isCodeGenOnly = 1 in {
|
||||
def t2LDM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
||||
|
@ -146,6 +146,20 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
|
||||
}
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
|
||||
defm VLDMD : vfp_ldst_d_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
|
||||
defm VLDMS : vfp_ldst_s_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
|
||||
} // mayLoad, hasExtraDefRegAllocReq
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
|
||||
defm VSTMD : vfp_ldst_d_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
|
||||
defm VSTMS : vfp_ldst_s_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
|
||||
} // mayStore, hasExtraSrcRegAllocReq
|
||||
|
||||
} // neverHasSideEffects
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
||||
isCodeGenOnly = 1 in {
|
||||
def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
||||
|
Loading…
Reference in New Issue
Block a user