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R600/SI: Fix fneg for 0.0

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V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michel Danzer
2014-02-04 07:12:38 +00:00
parent e2d1c6c19d
commit de2e0bc366
4 changed files with 87 additions and 18 deletions
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22
lib/Target/R600/SIInstructions.td
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@@ -1688,16 +1688,30 @@ def : Pat <
0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
>;
/********** ================================ **********/
/********** Floating point absolute/negative **********/
/********** ================================ **********/
// Manipulate the sign bit directly, as e.g. using the source negation modifier
// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
// breaking the piglit *s-floatBitsToInt-neg* tests
// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
// removing these patterns
def : Pat <
(fneg (fabs f32:$src)),
(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
>;
def : Pat <
(fabs f32:$src),
(V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
>;
def : Pat <
(fneg f32:$src),
(V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
>;
/********** ================== **********/