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[ARM] Add more pattern matching for f16 <-> f64 conversions

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Specifically when the conversion is done in two steps, f16 -> f32 -> f64.

For example:

%1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
%conv = fpext float %1 to double

to:

vcvtb.f64.f16


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2015-03-23 15:59:54 +00:00
parent cab2a096fd
commit de5be4657f
2 changed files with 39 additions and 0 deletions
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8
lib/Target/ARM/ARMInstrVFP.td
View File

@@ -627,6 +627,14 @@ def : Pat<(f16_to_fp GPR:$a),
def : Pat<(f64 (f16_to_fp GPR:$a)), def : Pat<(f64 (f16_to_fp GPR:$a)),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
def : Pat<(f64 (fextend (f16_to_fp GPR:$a))),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
def : Pat<(fp_to_f16 (fround (f64 DPR:$a))),
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
multiclass vcvt_inst<string opc, bits<2> rm, multiclass vcvt_inst<string opc, bits<2> rm,
SDPatternOperator node = null_frag> { SDPatternOperator node = null_frag> {
let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {

31
test/CodeGen/ARM/fp16-64.ll Normal file
View File

@@ -0,0 +1,31 @@
; RUN: llc -mtriple=arm -mattr=+fp-armv8 < %s | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=V8 %s
; RUN: llc -mtriple=arm -mattr=+vfp3,+d16 < %s | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=NOV8 %s
declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
define void @vcvt_f64_f16(i16* %x, double* %y) nounwind {
entry:
; CHECK-LABEL: vcvt_f64_f16
%0 = load i16, i16* %x, align 2
%1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
%conv = fpext float %1 to double
; CHECK-V8: vcvtb.f64.f16
; CHECK-NOV8-NOT: vcvtb.f64.f16
store double %conv, double* %y, align 8
ret void
}
define void @vcvt_f16_f64(i16* %x, double* %y) nounwind {
entry:
; CHECK-LABEL: vcvt_f16_f64
%0 = load double, double* %y, align 8
%conv = fptrunc double %0 to float
; CHECK-V8: vcvtb.f16.f64
; CHECK-NOV8-NOT: vcvtb.f16.f64
%1 = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
store i16 %1, i16* %x, align 2
ret void
}