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Change the x86 32-bit scheduler to register pressure and fix up the
corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -221,7 +221,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// X86 is weird, it always uses i8 for shift amounts and setcc results.
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setBooleanContents(ZeroOrOneBooleanContent);
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setSchedulingPreference(Sched::ILP);
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// For 64-bit since we have so many registers use the ILP scheduler, for
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// 32-bit code use the register pressure specific scheduling.
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if (Subtarget->is64Bit())
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setSchedulingPreference(Sched::ILP);
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else
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setSchedulingPreference(Sched::RegPressure);
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setStackPointerRegisterToSaveRestore(X86StackPtr);
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if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
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@ -1,4 +1,3 @@
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; XFAIL: *
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; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& \
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; RUN: not grep {Number of register spills}
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; END.
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@ -1,6 +1,6 @@
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; Check that eh_return & unwind_init were properly lowered
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; RUN: llc < %s | grep %ebp | count 7
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; RUN: llc < %s | grep %edx | count 5
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; RUN: llc < %s | grep %ecx | count 5
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "i386-pc-linux"
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep pcmpeqd | count 1
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; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
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; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
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; This testcase shouldn't need to spill the -1 value,
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@ -1,4 +1,3 @@
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; XFAIL: *
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; RUN: llc < %s -mcpu=i486 | grep fstpl | count 5
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; RUN: llc < %s -mcpu=i486 | grep fstps | count 2
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; PR1505
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@ -1,7 +1,7 @@
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; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s
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; CHECK: divps
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; CHECK: divss
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; CHECK: divps
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; CHECK: divps
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%vec = type <9 x float>
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define %vec @vecdiv( %vec %p1, %vec %p2)
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