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https://github.com/c64scene-ar/llvm-6502.git
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Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
and add some basic tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich
parent
d652b1368b
commit
de64aaf6c8
@ -4983,8 +4983,14 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned incr = MI->getOperand(2).getReg();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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if (isThumb2) {
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MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
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MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
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}
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unsigned ldrOpc, strOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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@ -5013,10 +5019,10 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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unsigned scratch2 = (!BinOpcode) ? incr :
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RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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TargetRegisterClass *TRC =
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isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
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// thisMBB:
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// ...
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@ -5079,8 +5085,14 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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unsigned incr = MI->getOperand(2).getReg();
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unsigned oldval = dest;
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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if (isThumb2) {
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MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
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MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
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}
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unsigned ldrOpc, strOpc, extendOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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@ -5112,9 +5124,10 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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unsigned scratch2 = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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TargetRegisterClass *TRC =
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isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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unsigned scratch = MRI.createVirtualRegister(TRC);
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unsigned scratch2 = MRI.createVirtualRegister(TRC);
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// thisMBB:
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// ...
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@ -5135,7 +5148,7 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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// Sign extend the value, if necessary.
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if (signExtend && extendOpc) {
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oldval = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
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oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
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AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest));
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}
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103
test/CodeGen/ARM/atomic-op.ll
Normal file
103
test/CodeGen/ARM/atomic-op.ll
Normal file
@ -0,0 +1,103 @@
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; RUN: llc < %s -mtriple=armv7-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
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define void @func(i32 %argc, i8** %argv) nounwind {
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entry:
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%argc.addr = alloca i32 ; <i32*> [#uses=1]
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%argv.addr = alloca i8** ; <i8***> [#uses=1]
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%val1 = alloca i32 ; <i32*> [#uses=2]
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%val2 = alloca i32 ; <i32*> [#uses=15]
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%andt = alloca i32 ; <i32*> [#uses=2]
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%ort = alloca i32 ; <i32*> [#uses=2]
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%xort = alloca i32 ; <i32*> [#uses=2]
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%old = alloca i32 ; <i32*> [#uses=18]
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%temp = alloca i32 ; <i32*> [#uses=2]
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store i32 %argc, i32* %argc.addr
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store i8** %argv, i8*** %argv.addr
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store i32 0, i32* %val1
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store i32 31, i32* %val2
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store i32 3855, i32* %andt
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store i32 3855, i32* %ort
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store i32 3855, i32* %xort
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store i32 4, i32* %temp
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%tmp = load i32* %temp
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; CHECK: ldrex
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; CHECK: add
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; CHECK: strex
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call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1]
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store i32 %0, i32* %old
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; CHECK: ldrex
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; CHECK: sub
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; CHECK: strex
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call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1]
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store i32 %1, i32* %old
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; CHECK: ldrex
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; CHECK: add
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; CHECK: strex
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call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1]
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store i32 %2, i32* %old
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; CHECK: ldrex
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; CHECK: sub
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; CHECK: strex
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call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1]
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store i32 %3, i32* %old
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; CHECK: ldrex
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; CHECK: and
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; CHECK: strex
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call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1]
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store i32 %4, i32* %old
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; CHECK: ldrex
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; CHECK: or
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; CHECK: strex
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call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1]
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store i32 %5, i32* %old
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; CHECK: ldrex
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; CHECK: eor
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; CHECK: strex
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call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1]
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store i32 %6, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1]
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store i32 %7, i32* %old
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%neg = sub i32 0, 1 ; <i32> [#uses=1]
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1]
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store i32 %8, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1]
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store i32 %9, i32* %old
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; CHECK: ldrex
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; CHECK: cmp
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; CHECK: strex
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call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1]
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store i32 %10, i32* %old
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ret void
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}
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declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
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declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
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