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Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -48,7 +48,7 @@ namespace ARMCC {
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AL
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};
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inline static CondCodes getOppositeCondition(CondCodes CC){
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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@ -67,7 +67,7 @@ namespace ARMCC {
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case LE: return GT;
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}
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}
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}
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} // namespace ARMCC
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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@ -90,6 +90,10 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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}
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}
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/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
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/// operations involving sub-registers.
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bool ModelWithRegSequence();
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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@ -164,6 +164,8 @@ private:
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectConcatVector(SDNode *N);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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@ -946,7 +948,7 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
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if (UseRegSeq) {
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if (llvm::ModelWithRegSequence()) {
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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@ -1481,6 +1483,21 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
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return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
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}
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SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
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// The only time a CONCAT_VECTORS operation can have legal types is when
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// two 64-bit vectors are concatenated to a 128-bit vector.
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EVT VT = N->getValueType(0);
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if (!VT.is128BitVector() || N->getNumOperands() != 2)
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llvm_unreachable("unexpected CONCAT_VECTORS");
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DebugLoc dl = N->getDebugLoc();
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SDValue V0 = N->getOperand(0);
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SDValue V1 = N->getOperand(1);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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@ -1972,6 +1989,10 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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}
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}
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case ISD::CONCAT_VECTORS: {
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return SelectConcatVector(N);
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}
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}
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return SelectCode(N);
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@ -1995,3 +2016,9 @@ FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new ARMDAGToDAGISel(TM, OptLevel);
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}
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/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
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/// operations involving sub-registers.
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bool llvm::ModelWithRegSequence() {
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return UseRegSeq;
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}
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@ -94,7 +94,10 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
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}
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setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
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if (llvm::ModelWithRegSequence())
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
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else
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setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
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setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
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