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Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-05 18:28:36 +00:00
parent d2c2d1809f
commit de8aa4ed9c
3 changed files with 38 additions and 4 deletions
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8
lib/Target/ARM/ARM.h
View File

@ -48,7 +48,7 @@ namespace ARMCC {
AL
};
inline static CondCodes getOppositeCondition(CondCodes CC){
inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
@ -67,7 +67,7 @@ namespace ARMCC {
case LE: return GT;
}
}
}
} // namespace ARMCC
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
@ -90,6 +90,10 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
}
}
/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
/// operations involving sub-registers.
bool ModelWithRegSequence();
FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOpt::Level OptLevel);

29
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -164,6 +164,8 @@ private:
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
SDNode *SelectConcatVector(SDNode *N);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
@ -946,7 +948,7 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
DebugLoc dl = V0.getNode()->getDebugLoc();
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
if (UseRegSeq) {
if (llvm::ModelWithRegSequence()) {
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
}
@ -1481,6 +1483,21 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
}
SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
// The only time a CONCAT_VECTORS operation can have legal types is when
// two 64-bit vectors are concatenated to a 128-bit vector.
EVT VT = N->getValueType(0);
if (!VT.is128BitVector() || N->getNumOperands() != 2)
llvm_unreachable("unexpected CONCAT_VECTORS");
DebugLoc dl = N->getDebugLoc();
SDValue V0 = N->getOperand(0);
SDValue V1 = N->getOperand(1);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
}
SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
@ -1972,6 +1989,10 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
}
}
}
case ISD::CONCAT_VECTORS: {
return SelectConcatVector(N);
}
}
return SelectCode(N);
@ -1995,3 +2016,9 @@ FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new ARMDAGToDAGISel(TM, OptLevel);
}
/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model
/// operations involving sub-registers.
bool llvm::ModelWithRegSequence() {
return UseRegSeq;
}

5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -94,7 +94,10 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
}
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
if (llvm::ModelWithRegSequence())
setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
else
setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);