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Eliminate a 'tst' that immediately follows an 'and'

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by morphing the 'and' to its recording form 'andS'.

This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.

I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Gabor Greif 2010-09-14 09:23:22 +00:00
parent 4e05b32509
commit de90bfd14a
1 changed files with 15 additions and 0 deletions
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15
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -1372,6 +1372,19 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
SrcReg = MI->getOperand(0).getReg();
CmpValue = MI->getOperand(1).getImm();
return true;
case ARM::TSTri: {
if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI))
return false;
const MachineInstr *AND = llvm::prior(MI);
if (AND->getOpcode() != ARM::ANDri)
return false;
if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
SrcReg = AND->getOperand(0).getReg();
CmpValue = 0;
return true;
}
}
}
return false;
@ -1421,6 +1434,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
switch (MI->getOpcode()) {
default: break;
case ARM::ADDri:
case ARM::ANDri:
case ARM::t2ANDri:
case ARM::SUBri:
case ARM::t2ADDri:
case ARM::t2SUBri: