From dea837d3c5179309642875dae6d2b20b5b4bd197 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 2 Sep 2014 06:23:54 +0000 Subject: [PATCH] [PowerPC] Guard against illegal selection of add for TargetConstant operands r208640 was reverted because it caused a self-hosting failure on ppc64. The underlying cause was the formation of ISD::ADD nodes with ISD::TargetConstant operands. Because we have no patterns for 'add' taking 'timm' nodes, these are selected as r+r add instructions (which is a miscompile). Guard against this kind of behavior in the future by making the backend crash should this occur (instead of silently generating invalid output). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216897 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 54ca2469fad..74f6b18fd03 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -908,6 +908,13 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) { return nullptr; // Already selected. } + // In case any misguided DAG-level optimizations form an ADD with a + // TargetConstant operand, crash here instead of miscompiling (by selecting + // an r+r add instead of some kind of r+i add). + if (N->getOpcode() == ISD::ADD && + N->getOperand(1).getOpcode() == ISD::TargetConstant) + llvm_unreachable("Invalid ADD with TargetConstant operand"); + switch (N->getOpcode()) { default: break;