mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
[Hexagon] Deleting old variants of intrinsics and adding missing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
ab9c16107e
commit
dec5091220
@ -596,6 +596,38 @@ def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
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def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
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def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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// Compare
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def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
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def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
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def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
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def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
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def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
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def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
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def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
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(i32 (C2_cmpgti (I32:$src1),
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(DEC_CONST_SIGNED s8ExtPred:$src2)))>;
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def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
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(i32 (C2_cmpgtui (I32:$src1),
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(DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
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// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
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def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
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(i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
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def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
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(I32:$src2))),
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(i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
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def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
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(I32:$src2))),
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(i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
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/********************************************************************
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* ALU64/ALU *
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*********************************************************************/
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@ -608,6 +640,10 @@ def: T_PP_pat<A2_andp, int_hexagon_A2_andp>;
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def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
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def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
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def: T_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>;
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def: T_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>;
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def: T_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>;
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def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
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def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
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@ -622,6 +658,27 @@ def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
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def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
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def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
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/********************************************************************
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* CR *
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*********************************************************************/
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class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
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Pat<(i32 (IntID IntRegs:$Rs)),
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(i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
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class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
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Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
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(i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
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def: qi_CRInst_qi_pat<C2_not, int_hexagon_C2_not>;
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def: qi_CRInst_qi_pat<C2_all8, int_hexagon_C2_all8>;
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def: qi_CRInst_qi_pat<C2_any8, int_hexagon_C2_any8>;
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def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>;
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def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>;
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def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>;
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def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>;
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def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>;
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// Multiply 32x32 and use lower result
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def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
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def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
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@ -1330,40 +1387,6 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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[],
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"$src1 = $dst">;
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/********************************************************************
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* ALU32/PERM *
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*********************************************************************/
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// ALU32 / PERM / Mux.
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def HEXAGON_C2_mux:
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si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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// ALU32 / PRED / Compare.
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def HEXAGON_C2_cmpeq:
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qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
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def HEXAGON_C2_cmpeqi:
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qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
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def HEXAGON_C2_cmpgei:
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qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
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def HEXAGON_C2_cmpgeui:
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qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
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def HEXAGON_C2_cmpgt:
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qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
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def HEXAGON_C2_cmpgti:
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qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
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def HEXAGON_C2_cmpgtu:
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qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
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def HEXAGON_C2_cmpgtui:
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qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
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def HEXAGON_C2_cmplt:
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qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
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def HEXAGON_C2_cmpltu:
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qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
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/********************************************************************
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* ALU32/VH *
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*********************************************************************/
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@ -1393,18 +1416,6 @@ def HEXAGON_A2_svsubhs:
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def HEXAGON_A2_svsubuhs:
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si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
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/********************************************************************
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* ALU64/ALU *
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*********************************************************************/
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// ALU64 / ALU / Compare.
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def HEXAGON_C2_cmpeqp:
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qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
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def HEXAGON_C2_cmpgtp:
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qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
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def HEXAGON_C2_cmpgtup:
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qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
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// ALU64 / ALU / Transfer register.
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def HEXAGON_A2_tfrp:
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di_ALU64_di <"", int_hexagon_A2_tfrp>;
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@ -1564,34 +1575,6 @@ def HEXAGON_A2_vsubw:
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def HEXAGON_A2_vsubws:
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di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
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/********************************************************************
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* CR *
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*********************************************************************/
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// CR / Logical reductions on predicates.
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def HEXAGON_C2_all8:
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qi_SInst_qi <"all8", int_hexagon_C2_all8>;
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def HEXAGON_C2_any8:
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qi_SInst_qi <"any8", int_hexagon_C2_any8>;
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// CR / Logical operations on predicates.
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def HEXAGON_C2_pxfer_map:
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qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
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def HEXAGON_C2_and:
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qi_SInst_qiqi <"and", int_hexagon_C2_and>;
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def HEXAGON_C2_andn:
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qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
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def HEXAGON_C2_not:
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qi_SInst_qi <"not", int_hexagon_C2_not>;
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def HEXAGON_C2_or:
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qi_SInst_qiqi <"or", int_hexagon_C2_or>;
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def HEXAGON_C2_orn:
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qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
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def HEXAGON_C2_xor:
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qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
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/********************************************************************
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* MTYPE/ALU *
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*********************************************************************/
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@ -206,103 +206,3 @@ def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
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def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
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def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
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class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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//
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// SInst Classes.
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//
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class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, !$src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, $src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, or($src2, !$src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, or($src2, $src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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// ALU32 / PRED / Conditional Shift Halfword.
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// ALU32 / PRED / Conditional Sign Extend.
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// ALU32 / PRED / Conditional Zero Extend.
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// ALU32 / PRED / Compare.
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def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
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def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
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def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
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def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
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def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
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def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
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/********************************************************************
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* CR *
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*********************************************************************/
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// CR / Corner Detection Acceleration.
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def Hexagon_C4_fastcorner9:
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qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
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def Hexagon_C4_fastcorner9_not:
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qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
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// CR / Logical Operations On Predicates.
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def Hexagon_C4_and_andn:
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qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
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def Hexagon_C4_and_and:
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qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
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def Hexagon_C4_and_orn:
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qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
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def Hexagon_C4_and_or:
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qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
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def Hexagon_C4_or_andn:
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qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
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def Hexagon_C4_or_and:
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qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
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def Hexagon_C4_or_orn:
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qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
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def Hexagon_C4_or_or:
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qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
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@ -17,6 +17,9 @@ def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>;
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def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
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def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
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def: qi_CRInst_qiqi_pat<C4_fastcorner9, int_hexagon_C4_fastcorner9>;
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def: qi_CRInst_qiqi_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>;
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def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
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def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
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@ -104,10 +107,6 @@ class di_MInst_diu4_rnd<string opc, Intrinsic IntID>
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
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def HEXAGON_C4_fastcorner9:
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qi_SInst_qiqi <"fastcorner9", int_hexagon_C4_fastcorner9>;
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def HEXAGON_C4_fastcorner9_not:
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qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>;
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def HEXAGON_M5_vrmpybuu:
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di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
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def HEXAGON_M5_vrmacbuu:
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@ -132,11 +131,3 @@ def HEXAGON_A5_vaddhubs:
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si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>;
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def HEXAGON_S5_vasrhrnd_goodsyntax:
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di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>;
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def HEXAGON_F2_sfcmpeq:
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qi_SInst_sfsf <"sfcmp.eq", int_hexagon_F2_sfcmpeq>;
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def HEXAGON_F2_sfcmpgt:
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qi_SInst_sfsf <"sfcmp.gt", int_hexagon_F2_sfcmpgt>;
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def HEXAGON_F2_sfcmpge:
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qi_SInst_sfsf <"sfcmp.ge", int_hexagon_F2_sfcmpge>;
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def HEXAGON_F2_sfcmpuo:
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qi_SInst_sfsf <"sfcmp.uo", int_hexagon_F2_sfcmpuo>;
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@ -2,6 +2,20 @@
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; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
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; Combine words into doubleword
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declare i64 @llvm.hexagon.A4.combineri(i32, i32)
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define i64 @A4_combineri(i32 %a) {
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%z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
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ret i64 %z
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}
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; CHECK: = combine(r0, #0)
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declare i64 @llvm.hexagon.A4.combineir(i32, i32)
|
||||
define i64 @A4_combineir(i32 %a) {
|
||||
%z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: = combine(#0, r0)
|
||||
|
||||
declare i64 @llvm.hexagon.A2.combineii(i32, i32)
|
||||
define i64 @A2_combineii() {
|
||||
%z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
|
||||
@ -59,6 +73,13 @@ define i32 @C2_muxir(i32 %a, i32 %b) {
|
||||
}
|
||||
; CHECK: r0 = mux(p0, r1, #0)
|
||||
|
||||
declare i32 @llvm.hexagon.C2.mux(i32, i32, i32)
|
||||
define i32 @C2_mux(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = mux(p0, r1, r2)
|
||||
|
||||
; Shift word by 16
|
||||
declare i32 @llvm.hexagon.A2.aslh(i32)
|
||||
define i32 @A2_aslh(i32 %a) {
|
||||
|
||||
@ -7,14 +7,14 @@ define i32 @C4_fastcorner9(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = fastcorner9(r0, r1)
|
||||
; CHECK: p0 = fastcorner9(p0, p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
|
||||
define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = !fastcorner9(r0, r1)
|
||||
; CHECK: p0 = !fastcorner9(p0, p1)
|
||||
|
||||
; Logical reductions on predicates
|
||||
declare i32 @llvm.hexagon.C2.any8(i32)
|
||||
@ -22,7 +22,7 @@ define i32 @C2_any8(i32 %a) {
|
||||
%z = call i32@llvm.hexagon.C2.any8(i32 %a)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = any8(r0)
|
||||
; CHECK: p0 = any8(p0)
|
||||
|
||||
declare i32 @llvm.hexagon.C2.all8(i32)
|
||||
define i32 @C2_all8(i32 %a) {
|
||||
@ -30,7 +30,7 @@ define i32 @C2_all8(i32 %a) {
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
; CHECK: p0 = all8(r0)
|
||||
; CHECK: p0 = all8(p0)
|
||||
|
||||
; Logical operations on predicates
|
||||
declare i32 @llvm.hexagon.C2.and(i32, i32)
|
||||
@ -38,39 +38,95 @@ define i32 @C2_and(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(r0, r1)
|
||||
; CHECK: p0 = and(p0, p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32)
|
||||
define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(p0, and(p1, p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C2.or(i32, i32)
|
||||
define i32 @C2_or(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(r0, r1)
|
||||
; CHECK: p0 = or(p0, p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32)
|
||||
define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(p0, or(p1, p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C2.xor(i32, i32)
|
||||
define i32 @C2_xor(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = xor(r0, r1)
|
||||
; CHECK: p0 = xor(p0, p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32)
|
||||
define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(p0, and(p1, p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C2.andn(i32, i32)
|
||||
define i32 @C2_andn(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(r0, !r1)
|
||||
; CHECK: p0 = and(p0, !p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32)
|
||||
define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(p0, or(p1, p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
|
||||
define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(p0, and(p1, !p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
|
||||
define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = and(p0, or(p1, !p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C2.not(i32)
|
||||
define i32 @C2_not(i32 %a) {
|
||||
%z = call i32@llvm.hexagon.C2.not(i32 %a)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = not(r0)
|
||||
; CHECK: p0 = not(p0)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
|
||||
define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(p0, and(p1, !p2))
|
||||
|
||||
declare i32 @llvm.hexagon.C2.orn(i32, i32)
|
||||
define i32 @C2_orn(i32 %a, i32 %b) {
|
||||
%z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(r0, !r1)
|
||||
; CHECK: p0 = or(p0, !p1)
|
||||
|
||||
declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
|
||||
define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) {
|
||||
%z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: p0 = or(p0, or(p1, !p2))
|
||||
|
||||
@ -543,3 +543,11 @@ define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) {
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = sub(r0.h, r1.h):sat:<<16
|
||||
|
||||
; Sign extend word to doubleword
|
||||
declare i64 @llvm.hexagon.A2.sxtw(i32)
|
||||
define i64 @A2_sxtw(i32 %a) {
|
||||
%z = call i64 @llvm.hexagon.A2.sxtw(i32 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: = sxtw(r0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user