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Use movq to move 64 bits in and out of mmx registers.
Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4447,6 +4447,11 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
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Op.getOperand(0))));
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if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
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return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64,
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Op.getOperand(0)));
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SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
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MVT VT = MVT::v2i32;
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switch (Op.getValueType().getSimpleVT()) {
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@ -163,10 +163,14 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[]>;
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let neverHasSideEffects = 1 in
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def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
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let neverHasSideEffects = 1 in {
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def MMX_MOVD64from64rr : MMXRI<0x7F, MRMDestReg,
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(outs GR64:$dst), (ins VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>;
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"movq\t{$src, $dst|$dst, $src}", []>;
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def MMX_MOVD64rrv164 : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (v1i64 (scalar_to_vector GR64:$src)))]>;
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}
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let neverHasSideEffects = 1 in
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def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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10
test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
Normal file
10
test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
Normal file
@ -0,0 +1,10 @@
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; RUN: llvm-as < %s | llc -march=x86-64
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; PR4669
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declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
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define <1 x i64> @test(i64 %t) {
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entry:
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%t1 = insertelement <1 x i64> undef, i64 %t, i32 0
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%t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48)
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ret <1 x i64> %t2
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}
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 4
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; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | count 8
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define i64 @foo(<1 x i64>* %p) {
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%t = load <1 x i64>* %p
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