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Coalesce subreg-subreg copies.

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At least some of them:

  %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2

Previously, we couldn't figure out that the above copy could be
eliminated by coalescing %vreg2 with %vreg1:sub_32bit.

The new getCommonSuperRegClass() hook makes it possible.

This is not very useful yet since the unmodified part of the destination
register usually interferes with the source register. The coalescer
needs to understand sub-register interference checking first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-07 22:57:55 +00:00
parent 7e56e92a33
commit defa0afa14
1 changed files with 25 additions and 14 deletions
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31
lib/CodeGen/RegisterCoalescer.cpp
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@ -258,24 +258,35 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
} }
} else { } else {
// Both registers are virtual. // Both registers are virtual.
const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
// Both registers have subreg indices. // Both registers have subreg indices.
if (SrcSub && DstSub) { if (SrcSub && DstSub) {
// For now we only handle the case of identical indices in commensurate unsigned SrcPre, DstPre;
// registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
// FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg. SrcPre, DstPre);
if (SrcSub != DstSub) if (!NewRC)
return false; return false;
const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); // We cannot handle the case where both Src and Dst would be a
if (!TRI.getCommonSubClass(DstRC, SrcRC)) // sub-register. Yet.
if (SrcPre && DstPre) {
DEBUG(dbgs() << "\tCannot handle " << NewRC->getName()
<< " with subregs " << TRI.getSubRegIndexName(SrcPre)
<< " and " << TRI.getSubRegIndexName(DstPre) << '\n');
return false; return false;
SrcSub = DstSub = 0; }
// One of these will be 0, so one register is a sub-register of the other.
SrcSub = DstPre;
DstSub = SrcPre;
} }
// There can be no SrcSub. // There can be no SrcSub.
if (SrcSub) { if (SrcSub) {
std::swap(Src, Dst); std::swap(Src, Dst);
std::swap(SrcRC, DstRC);
DstSub = SrcSub; DstSub = SrcSub;
SrcSub = 0; SrcSub = 0;
assert(!Flipped && "Unexpected flip"); assert(!Flipped && "Unexpected flip");
@ -283,12 +294,12 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
} }
// Find the new register class. // Find the new register class.
const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); if (!NewRC) {
const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
if (DstSub) if (DstSub)
NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
else else
NewRC = TRI.getCommonSubClass(DstRC, SrcRC); NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
}
if (!NewRC) if (!NewRC)
return false; return false;
CrossClass = NewRC != DstRC || NewRC != SrcRC; CrossClass = NewRC != DstRC || NewRC != SrcRC;