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Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138012 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
2bd6269417
commit
df01610d6f
@ -1840,23 +1840,17 @@ multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
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}
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/// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F32Int> {
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multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
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def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, XS, Requires<[HasAVX, OptForSize]>;
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def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins ssmem:$src1, VR128:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
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[(set VR128:$dst, (F32Int VR128:$src))]>;
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
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!strconcat(OpcodeStr,
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"ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
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[(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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}
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/// sse1_fp_unop_p - SSE1 unops in packed form.
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@ -1921,21 +1915,17 @@ multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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}
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/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int> {
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multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
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def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
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(ins FR64:$src1, f64mem:$src2),
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def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
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def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
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[(set VR128:$dst, (F64Int VR128:$src))]>;
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def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
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[(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
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}
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/// sse2_fp_unop_p - SSE2 unops in vector forms.
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@ -1983,9 +1973,8 @@ multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
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let Predicates = [HasAVX] in {
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// Square root.
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defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
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sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
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VEX_4V;
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defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
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sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
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defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
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sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
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@ -1999,15 +1988,13 @@ let Predicates = [HasAVX] in {
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
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int_x86_sse_rsqrt_ss>, VEX_4V;
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defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
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defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
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sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
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sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
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sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
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VEX_4V;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
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defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
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sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
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sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
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@ -2016,15 +2003,61 @@ let Predicates = [HasAVX] in {
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def : Pat<(f32 (fsqrt FR32:$src)),
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(VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
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def : Pat<(f32 (fsqrt (load addr:$src))),
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(VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX, OptForSize]>;
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def : Pat<(f64 (fsqrt FR64:$src)),
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(VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
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def : Pat<(f64 (fsqrt (load addr:$src))),
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(VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX, OptForSize]>;
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def : Pat<(f32 (fsqrt (load addr:$src))),
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(VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
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def : Pat<(f32 (X86frsqrt FR32:$src)),
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(VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
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def : Pat<(f32 (X86frsqrt (load addr:$src))),
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(VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX, OptForSize]>;
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def : Pat<(f32 (X86frcp FR32:$src)),
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(VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
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def : Pat<(f32 (X86frcp (load addr:$src))),
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(VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX, OptForSize]>;
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let Predicates = [HasAVX] in {
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def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
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(VSQRTSSr (f32 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
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sub_ss)>;
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def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
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(VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
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(VSQRTSDr (f64 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
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sub_sd)>;
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def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
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(VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
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def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
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(VRSQRTSSr (f32 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
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sub_ss)>;
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def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
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(VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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def : Pat<(int_x86_sse_rcp_ss VR128:$src),
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
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(VRCPSSr (f32 (IMPLICIT_DEF)),
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(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
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sub_ss)>;
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def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
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(VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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}
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// Square root.
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defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
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sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
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