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[AArch64] Use intermediate step for concat_vectors of illegal truncs.

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Optimize concat_vectors of truncated vectors, where the intermediate
type is illegal, to avoid said illegality,  e.g.,
  (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
                         (v2i16 (truncate (v2i64)))))
->
  (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
                                          (v2i32 (truncate (v2i64)))))))

This isn't really target-specific, and, as such, would best go in the
DAGCombiner.  However, ISD::TRUNCATE legality isn't keyed on both input
and result type, so we might generate worse code when we don't know
better.  On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
rdar://20022387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232459 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2015-03-17 03:23:09 +00:00
parent 1c48733f54
commit df08543f48
2 changed files with 62 additions and 0 deletions
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31
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7180,6 +7180,37 @@ static SDValue performConcatVectorsCombine(SDNode *N,
EVT VT = N->getValueType(0);
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
// Optimize concat_vectors of truncated vectors, where the intermediate
// type is illegal, to avoid said illegality, e.g.,
// (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
// (v2i16 (truncate (v2i64)))))
// ->
// (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
// (v2i32 (truncate (v2i64)))))))
// This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
// on both input and result type, so we might generate worse code.
// On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
if (N->getNumOperands() == 2 &&
N0->getOpcode() == ISD::TRUNCATE &&
N1->getOpcode() == ISD::TRUNCATE) {
SDValue N00 = N0->getOperand(0);
SDValue N10 = N1->getOperand(0);
EVT N00VT = N00.getValueType();
if (N00VT == N10.getValueType() &&
(N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v2i32 : MVT::v4i16);
MVT ConcatMidVT = MVT::getVectorVT(MidVT.getVectorElementType(),
MidVT.getVectorNumElements() * 2);
return DAG.getNode(
ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatMidVT,
DAG.getNode(ISD::TRUNCATE, dl, MidVT, N00),
DAG.getNode(ISD::TRUNCATE, dl, MidVT, N10)));
}
}
// Wait 'til after everything is legalized to try this. That way we have
// legal vector types and such.
if (DCI.isBeforeLegalizeOps())

31
test/CodeGen/AArch64/concat_vector-truncate-combine.ll Normal file
View File

@ -0,0 +1,31 @@
; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
entry:
; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
; CHECK-NEXT: xtn.2s v0, v0
; CHECK-NEXT: xtn2.4s v0, v1
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: ret
%at = trunc <2 x i64> %a to <2 x i16>
%bt = trunc <2 x i64> %b to <2 x i16>
%shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i16> %shuffle
}
define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
entry:
; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: xtn2.8h v0, v1
; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: ret
%at = trunc <4 x i32> %a to <4 x i8>
%bt = trunc <4 x i32> %b to <4 x i8>
%shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %shuffle
}
attributes #0 = { nounwind }