6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-07 16:42:07 +00:00
Code Issues Projects Releases Wiki Activity

Fix the register scavenger for targets that provide custom spilling

Browse Source 
As pointed out by Richard Sandiford, my recent updates to the register
scavenger broke targets that use custom spilling (because the new code assumed
that if there were no valid spill slots, than spilling would be impossible).

I don't have a test case, but it should be possible to create one for Thumb 1,
Mips 16, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-26 21:20:15 +00:00
parent aa6047d23d
commit df23a60fa6
2 changed files with 8 additions and 4 deletions
include/llvm/CodeGen
RegisterScavenging.h
lib/CodeGen
RegisterScavenging.cpp

5
include/llvm/CodeGen/RegisterScavenging.h

@ -42,7 +42,7 @@ class RegScavenger {
/// Information on scavenged registers (held in a spill slot).
struct ScavengedInfo {
ScavengedInfo(int FI) : FrameIndex(FI), Reg(0), Restore(NULL) {}
ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
/// A spill slot used for scavenging a register post register allocation.
int FrameIndex;
@ -130,7 +130,8 @@ public:
void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin(),
IE = Scavenged.end(); I != IE; ++I)
A.push_back(I->FrameIndex);
if (I->FrameIndex >= 0)
A.push_back(I->FrameIndex);
}
/// scavengeRegister - Make a register of the specific register class

7
lib/CodeGen/RegisterScavenging.cpp

@ -371,8 +371,11 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
if (Scavenged[SI].Reg == 0)
break;
assert(SI < Scavenged.size() &&
"Scavenger slots are live, unable to scavenge another register!");
if (SI < Scavenged.size()) {
// We need to scavenge a register but have no spill slot, the target
// must know how to do it (if not, we'll assert below).
Scavenged.push_back(ScavengedInfo());
}
// Avoid infinite regress
Scavenged[SI].Reg = SReg;