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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
b49fb7bcd5
commit
df4626ef15
@ -11,6 +11,12 @@
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#ifndef SIDEFINES_H_
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#define SIDEFINES_H_
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namespace SIInstrFlags {
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enum {
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MIMG = 1 << 3
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};
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}
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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@ -1022,9 +1022,11 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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/// \brief Fold the instructions after slecting them
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SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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SelectionDAG &DAG) const {
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
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Node = AdjustRegClass(Node, DAG);
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if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1)
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if (TII->isMIMG(Node->getMachineOpcode()))
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adjustWritemask(Node, DAG);
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return foldOperands(Node, DAG);
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@ -1034,7 +1036,9 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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/// bits set in the writemask
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void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const {
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if (AMDGPU::isMIMG(MI->getOpcode()) == -1)
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
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if (!TII->isMIMG(MI->getOpcode()))
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return;
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unsigned VReg = MI->getOperand(0).getReg();
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@ -17,10 +17,12 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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field bits<1> VM_CNT = 0;
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field bits<1> EXP_CNT = 0;
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field bits<1> LGKM_CNT = 0;
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field bits<1> MIMG = 0;
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let TSFlags{0} = VM_CNT;
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let TSFlags{1} = EXP_CNT;
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let TSFlags{2} = LGKM_CNT;
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let TSFlags{3} = MIMG;
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}
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class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
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@ -414,6 +416,7 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let MIMG = 1;
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}
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def EXP : Enc64<
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@ -15,6 +15,7 @@
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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@ -224,6 +225,10 @@ SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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int SIInstrInfo::isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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//===----------------------------------------------------------------------===//
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// Indirect addressing callbacks
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//===----------------------------------------------------------------------===//
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@ -47,6 +47,7 @@ public:
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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int isMIMG(uint16_t Opcode) const;
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virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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@ -80,7 +81,6 @@ namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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int isMIMG(uint16_t Opcode);
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} // End namespace AMDGPU
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@ -397,11 +397,12 @@ class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF
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let mayStore = 0;
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}
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class MIMG_NoSampler_Helper <bits<7> op, string asm> : MIMG <
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class MIMG_NoSampler_Helper <bits<7> op, string asm,
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RegisterClass src_rc> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, unknown:$vaddr,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
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SReg_256:$srsrc),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc",
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@ -412,11 +413,18 @@ class MIMG_NoSampler_Helper <bits<7> op, string asm> : MIMG <
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let hasPostISelHook = 1;
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}
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class MIMG_Sampler_Helper <bits<7> op, string asm> : MIMG <
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multiclass MIMG_NoSampler <bits<7> op, string asm> {
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def _V1 : MIMG_NoSampler_Helper <op, asm, VReg_32>;
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def _V2 : MIMG_NoSampler_Helper <op, asm, VReg_64>;
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def _V4 : MIMG_NoSampler_Helper <op, asm, VReg_128>;
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}
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class MIMG_Sampler_Helper <bits<7> op, string asm,
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RegisterClass src_rc> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, unknown:$vaddr,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
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SReg_256:$srsrc, SReg_128:$ssamp),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
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@ -426,6 +434,14 @@ class MIMG_Sampler_Helper <bits<7> op, string asm> : MIMG <
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let hasPostISelHook = 1;
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}
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multiclass MIMG_Sampler <bits<7> op, string asm> {
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def _V1 : MIMG_Sampler_Helper <op, asm, VReg_32>;
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def _V2 : MIMG_Sampler_Helper <op, asm, VReg_64>;
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def _V4 : MIMG_Sampler_Helper <op, asm, VReg_128>;
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def _V8 : MIMG_Sampler_Helper <op, asm, VReg_256>;
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def _V16 : MIMG_Sampler_Helper <op, asm, VReg_512>;
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}
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//===----------------------------------------------------------------------===//
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// Vector instruction mappings
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//===----------------------------------------------------------------------===//
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@ -457,13 +473,4 @@ def getCommuteOrig : InstrMapping {
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let ValueCols = [["1"]];
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}
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// Test if the supplied opcode is an MIMG instruction
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def isMIMG : InstrMapping {
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let FilterClass = "MIMG";
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let RowFields = ["Inst"];
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let ColFields = ["Size"];
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let KeyCol = ["8"];
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let ValueCols = [["8"]];
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}
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include "SIInstructions.td"
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@ -500,8 +500,8 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
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//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
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//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
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def IMAGE_LOAD : MIMG_NoSampler_Helper <0x00000000, "IMAGE_LOAD">;
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def IMAGE_LOAD_MIP : MIMG_NoSampler_Helper <0x00000001, "IMAGE_LOAD_MIP">;
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defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
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defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
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//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
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//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
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//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
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@ -510,7 +510,7 @@ def IMAGE_LOAD_MIP : MIMG_NoSampler_Helper <0x00000001, "IMAGE_LOAD_MIP">;
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//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
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//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
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//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
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def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO">;
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def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO", VReg_32>;
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//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
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//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
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//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
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@ -528,20 +528,20 @@ def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO">;
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//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
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//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
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//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
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def IMAGE_SAMPLE : MIMG_Sampler_Helper <0x00000020, "IMAGE_SAMPLE">;
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defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
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//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
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def IMAGE_SAMPLE_D : MIMG_Sampler_Helper <0x00000022, "IMAGE_SAMPLE_D">;
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defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
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//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
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def IMAGE_SAMPLE_L : MIMG_Sampler_Helper <0x00000024, "IMAGE_SAMPLE_L">;
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def IMAGE_SAMPLE_B : MIMG_Sampler_Helper <0x00000025, "IMAGE_SAMPLE_B">;
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defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
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defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
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//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
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//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
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def IMAGE_SAMPLE_C : MIMG_Sampler_Helper <0x00000028, "IMAGE_SAMPLE_C">;
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defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
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//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
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def IMAGE_SAMPLE_C_D : MIMG_Sampler_Helper <0x0000002a, "IMAGE_SAMPLE_C_D">;
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defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
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//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
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def IMAGE_SAMPLE_C_L : MIMG_Sampler_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">;
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def IMAGE_SAMPLE_C_B : MIMG_Sampler_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">;
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defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
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defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
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//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
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//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
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//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
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@ -1327,7 +1327,7 @@ def : Pat <
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/* int_SI_sample for simple 1D texture lookup */
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def : Pat <
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(int_SI_sample v1i32:$addr, v32i8:$rsrc, v16i8:$sampler, imm),
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(IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
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(IMAGE_SAMPLE_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
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>;
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class SamplePattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat <
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@ -1358,33 +1358,51 @@ class SampleShadowArrayPattern<Intrinsic name, MIMG opcode,
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>;
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/* int_SI_sample* for texture lookups consuming more address parameters */
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multiclass SamplePatterns<ValueType addr_type> {
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def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_type>;
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def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>;
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def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>;
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def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>;
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multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
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MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
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MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
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def : SamplePattern <int_SI_sample, sample, addr_type>;
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def : SampleRectPattern <int_SI_sample, sample, addr_type>;
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def : SampleArrayPattern <int_SI_sample, sample, addr_type>;
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def : SampleShadowPattern <int_SI_sample, sample_c, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sample, sample_c, addr_type>;
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def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>;
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def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>;
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def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>;
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def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>;
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def : SamplePattern <int_SI_samplel, sample_l, addr_type>;
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def : SampleArrayPattern <int_SI_samplel, sample_l, addr_type>;
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def : SampleShadowPattern <int_SI_samplel, sample_c_l, addr_type>;
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def : SampleShadowArrayPattern <int_SI_samplel, sample_c_l, addr_type>;
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def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>;
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def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>;
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def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>;
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def : SamplePattern <int_SI_sampleb, sample_b, addr_type>;
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def : SampleArrayPattern <int_SI_sampleb, sample_b, addr_type>;
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def : SampleShadowPattern <int_SI_sampleb, sample_c_b, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sampleb, sample_c_b, addr_type>;
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def : SamplePattern <int_SI_sampled, IMAGE_SAMPLE_D, addr_type>;
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def : SampleArrayPattern <int_SI_sampled, IMAGE_SAMPLE_D, addr_type>;
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def : SampleShadowPattern <int_SI_sampled, IMAGE_SAMPLE_C_D, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sampled, IMAGE_SAMPLE_C_D, addr_type>;
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def : SamplePattern <int_SI_sampled, sample_d, addr_type>;
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def : SampleArrayPattern <int_SI_sampled, sample_d, addr_type>;
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def : SampleShadowPattern <int_SI_sampled, sample_c_d, addr_type>;
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def : SampleShadowArrayPattern <int_SI_sampled, sample_c_d, addr_type>;
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}
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defm : SamplePatterns<v2i32>;
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defm : SamplePatterns<v4i32>;
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defm : SamplePatterns<v8i32>;
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defm : SamplePatterns<v16i32>;
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defm : SamplePatterns<IMAGE_SAMPLE_V2, IMAGE_SAMPLE_C_V2,
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IMAGE_SAMPLE_L_V2, IMAGE_SAMPLE_C_L_V2,
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IMAGE_SAMPLE_B_V2, IMAGE_SAMPLE_C_B_V2,
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IMAGE_SAMPLE_D_V2, IMAGE_SAMPLE_C_D_V2,
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v2i32>;
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defm : SamplePatterns<IMAGE_SAMPLE_V4, IMAGE_SAMPLE_C_V4,
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IMAGE_SAMPLE_L_V4, IMAGE_SAMPLE_C_L_V4,
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IMAGE_SAMPLE_B_V4, IMAGE_SAMPLE_C_B_V4,
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IMAGE_SAMPLE_D_V4, IMAGE_SAMPLE_C_D_V4,
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v4i32>;
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defm : SamplePatterns<IMAGE_SAMPLE_V8, IMAGE_SAMPLE_C_V8,
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IMAGE_SAMPLE_L_V8, IMAGE_SAMPLE_C_L_V8,
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IMAGE_SAMPLE_B_V8, IMAGE_SAMPLE_C_B_V8,
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IMAGE_SAMPLE_D_V8, IMAGE_SAMPLE_C_D_V8,
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v8i32>;
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defm : SamplePatterns<IMAGE_SAMPLE_V16, IMAGE_SAMPLE_C_V16,
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IMAGE_SAMPLE_L_V16, IMAGE_SAMPLE_C_L_V16,
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IMAGE_SAMPLE_B_V16, IMAGE_SAMPLE_C_B_V16,
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IMAGE_SAMPLE_D_V16, IMAGE_SAMPLE_C_D_V16,
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v16i32>;
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/* int_SI_imageload for texture fetches consuming varying address parameters */
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class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
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@ -1407,15 +1425,21 @@ class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type
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(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
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>;
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multiclass ImageLoadPatterns<ValueType addr_type> {
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def : ImageLoadPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>;
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def : ImageLoadArrayPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>;
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def : ImageLoadMSAAPattern <int_SI_imageload, IMAGE_LOAD, addr_type>;
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def : ImageLoadArrayMSAAPattern <int_SI_imageload, IMAGE_LOAD, addr_type>;
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multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
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def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
|
||||
def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
|
||||
}
|
||||
|
||||
defm : ImageLoadPatterns<v2i32>;
|
||||
defm : ImageLoadPatterns<v4i32>;
|
||||
multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
|
||||
def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
|
||||
def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
|
||||
}
|
||||
|
||||
defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V2, v2i32>;
|
||||
defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4, v4i32>;
|
||||
|
||||
defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V2, v2i32>;
|
||||
defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4, v4i32>;
|
||||
|
||||
/* Image resource information */
|
||||
def : Pat <
|
||||
|
||||
@ -82,6 +82,50 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that ccordinates are stored in vgprs and not sgprs
|
||||
; CHECK: vgpr_coords
|
||||
; CHECK: IMAGE_LOAD_MIP VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 15, 0, 0, 0, 0, 0, 0, 0, VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}
|
||||
define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
%20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
|
||||
%21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
|
||||
%22 = getelementptr float addrspace(2)* %21, i32 0
|
||||
%23 = load float addrspace(2)* %22, !tbaa !0, !invariant.load !1
|
||||
%24 = getelementptr float addrspace(2)* %21, i32 1
|
||||
%25 = load float addrspace(2)* %24, !tbaa !0, !invariant.load !1
|
||||
%26 = getelementptr float addrspace(2)* %21, i32 4
|
||||
%27 = load float addrspace(2)* %26, !tbaa !0, !invariant.load !1
|
||||
%28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
|
||||
%29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
|
||||
%30 = bitcast float %27 to i32
|
||||
%31 = bitcast float %23 to i32
|
||||
%32 = bitcast float %25 to i32
|
||||
%33 = insertelement <4 x i32> undef, i32 %31, i32 0
|
||||
%34 = insertelement <4 x i32> %33, i32 %32, i32 1
|
||||
%35 = insertelement <4 x i32> %34, i32 %30, i32 2
|
||||
%36 = insertelement <4 x i32> %35, i32 undef, i32 3
|
||||
%37 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> %36, <32 x i8> %29, i32 2)
|
||||
%38 = extractelement <4 x i32> %37, i32 0
|
||||
%39 = extractelement <4 x i32> %37, i32 1
|
||||
%40 = extractelement <4 x i32> %37, i32 2
|
||||
%41 = extractelement <4 x i32> %37, i32 3
|
||||
%42 = bitcast i32 %38 to float
|
||||
%43 = bitcast i32 %39 to float
|
||||
%44 = bitcast i32 %40 to float
|
||||
%45 = bitcast i32 %41 to float
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %42, float %43, float %44, float %45)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.SI.imageload.(<4 x i32>, <8 x i32>, i32) readnone
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1
|
||||
|
||||
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
|
||||
|
||||
attributes #0 = { "ShaderType"="0" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
!0 = metadata !{metadata !"const", null, i32 1}
|
||||
!1 = metadata !{}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user