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start using PPC predicates more consistently.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-17 22:10:59 +00:00
parent b1409ce7ba
commit df4ed6350b
10 changed files with 118 additions and 60 deletions
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15
lib/Target/PowerPC/PPC.h
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@ -27,21 +27,6 @@ namespace llvm {
class FunctionPass;
class MachineCodeEmitter;
namespace PPC {
/// Predicate - These are "(BI << 5) | BO" for various predicates.
enum Predicate {
PRED_ALWAYS = (0 << 5) | 20,
PRED_LT = (0 << 5) | 12,
PRED_LE = (1 << 5) | 4,
PRED_EQ = (2 << 5) | 12,
PRED_GE = (0 << 5) | 4,
PRED_GT = (1 << 5) | 12,
PRED_NE = (2 << 5) | 4,
PRED_UN = (3 << 5) | 12,
PRED_NU = (3 << 5) | 4
};
}
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCAsmPrinterPass(std::ostream &OS,

1
lib/Target/PowerPC/PPCAsmPrinter.cpp
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@ -18,6 +18,7 @@
#define DEBUG_TYPE "asmprinter"
#include "PPC.h"
#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCSubtarget.h"
#include "llvm/Constants.h"

28
lib/Target/PowerPC/PPCBranchSelector.cpp
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@ -18,6 +18,7 @@
#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCInstrInfo.h"
#include "PPCPredicates.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetAsmInfo.h"
@ -125,19 +126,36 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
// 1. PPC branch opcode
// 2. Target MBB
MachineBasicBlock *DestMBB = MBBI->getOperand(2).getMachineBasicBlock();
unsigned Opcode = MBBI->getOperand(1).getImmedValue();
PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(1).getImm();
unsigned CRReg = MBBI->getOperand(0).getReg();
int Displacement = OffsetMap[DestMBB->getNumber()] - ByteCount;
unsigned Inverted = PPCInstrInfo::invertPPCBranchOpcode(Opcode);
bool ShortBranchOk = Displacement >= -32768 && Displacement <= 32767;
// Branch on opposite condition if a short branch isn't ok.
if (!ShortBranchOk)
Pred = PPC::InvertPredicate(Pred);
unsigned Opcode;
switch (Pred) {
default: assert(0 && "Unknown cond branch predicate!");
case PPC::PRED_LT: Opcode = PPC::BLT; break;
case PPC::PRED_LE: Opcode = PPC::BLE; break;
case PPC::PRED_EQ: Opcode = PPC::BEQ; break;
case PPC::PRED_GE: Opcode = PPC::BGE; break;
case PPC::PRED_GT: Opcode = PPC::BGT; break;
case PPC::PRED_NE: Opcode = PPC::BNE; break;
case PPC::PRED_UN: Opcode = PPC::BUN; break;
case PPC::PRED_NU: Opcode = PPC::BNU; break;
}
MachineBasicBlock::iterator MBBJ;
if (Displacement >= -32768 && Displacement <= 32767) {
if (ShortBranchOk) {
MBBJ = BuildMI(*MBB, MBBI, Opcode, 2).addReg(CRReg).addMBB(DestMBB);
} else {
// Long branch, skip next branch instruction (i.e. $PC+8).
++NumExpanded;
BuildMI(*MBB, MBBI, Inverted, 2).addReg(CRReg).addImm(2);
BuildMI(*MBB, MBBI, Opcode, 2).addReg(CRReg).addImm(2);
MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
}

26
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "PPC.h"
#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCISelLowering.h"
#include "PPCHazardRecognizers.h"
@ -594,34 +595,31 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
/// to Condition.
static unsigned getBCCForSetCC(ISD::CondCode CC) {
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
case ISD::SETUEQ:
case ISD::SETEQ: return PPC::BEQ;
case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETONE: // FIXME: This is incorrect see PR642.
case ISD::SETUNE:
case ISD::SETNE: return PPC::BNE;
case ISD::SETNE: return PPC::PRED_NE;
case ISD::SETOLT: // FIXME: This is incorrect see PR642.
case ISD::SETULT:
case ISD::SETLT: return PPC::BLT;
case ISD::SETLT: return PPC::PRED_LT;
case ISD::SETOLE: // FIXME: This is incorrect see PR642.
case ISD::SETULE:
case ISD::SETLE: return PPC::BLE;
case ISD::SETLE: return PPC::PRED_LE;
case ISD::SETOGT: // FIXME: This is incorrect see PR642.
case ISD::SETUGT:
case ISD::SETGT: return PPC::BGT;
case ISD::SETGT: return PPC::PRED_GT;
case ISD::SETOGE: // FIXME: This is incorrect see PR642.
case ISD::SETUGE:
case ISD::SETGE: return PPC::BGE;
case ISD::SETGE: return PPC::PRED_GE;
case ISD::SETO: return PPC::BNU;
case ISD::SETUO: return PPC::BUN;
case ISD::SETO: return PPC::PRED_NU;
case ISD::SETUO: return PPC::PRED_UN;
}
return 0;
}
/// getCRIdxForSetCC - Return the index of the condition register field
@ -983,7 +981,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
}
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
unsigned BROpc = getBCCForSetCC(CC);
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
if (N->getValueType(0) == MVT::i32)
@ -1007,7 +1005,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)),
SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
}

16
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -13,6 +13,7 @@
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCPerfectShuffle.h"
#include "llvm/ADT/VectorExtras.h"
@ -2611,8 +2612,9 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *thisMBB = BB;
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
unsigned SelectPred = MI->getOperand(4).getImm();
BuildMI(BB, PPC::COND_BRANCH, 3)
.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@ -2870,20 +2872,20 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
// Unpack the result based on how the target uses it.
unsigned CompOpc;
PPC::Predicate CompOpc;
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
default: // Can't happen, don't crash on invalid number though.
case 0: // Branch on the value of the EQ bit of CR6.
CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
break;
case 1: // Branch on the inverted value of the EQ bit of CR6.
CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
break;
case 2: // Branch on the value of the LT bit of CR6.
CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
break;
case 3: // Branch on the inverted value of the LT bit of CR6.
CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
break;
}

3
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "PPCInstrInfo.h"
#include "PPCPredicates.h"
#include "PPCGenInstrInfo.inc"
#include "PPCTargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@ -284,6 +285,6 @@ bool PPCInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
// Leave the CR# the same, but invert the condition.
Cond[1].setImm(invertPPCBranchOpcode(Cond[1].getImm()));
Cond[1].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[1].getImm()));
return false;
}

16
lib/Target/PowerPC/PPCInstrInfo.h
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@ -112,22 +112,6 @@ public:
const std::vector<MachineOperand> &Cond) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC branch opcode!");
case PPC::BEQ: return PPC::BNE;
case PPC::BNE: return PPC::BEQ;
case PPC::BLT: return PPC::BGE;
case PPC::BGE: return PPC::BLT;
case PPC::BGT: return PPC::BLE;
case PPC::BLE: return PPC::BGT;
case PPC::BNU: return PPC::BUN;
case PPC::BUN: return PPC::BNU;
}
}
};
}

4
lib/Target/PowerPC/PPCInstrInfo.td
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@ -338,8 +338,7 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
def BLR : XLForm_2_br<19, 16, 0,
(ops pred:$p),
def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p),
"b${p:cc}lr ${p:reg}", BrB,
[(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
@ -354,6 +353,7 @@ let Defs = [LR] in
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
noResults = 1, PPC970_Unit = 7 in {
// COND_BRANCH is formed before branch selection, it is turned into Bcc below.
// 'opc' is a 'PPC::Predicate' value.
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
"${:comment} COND_BRANCH $crS, $opc, $dst",
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;

30
lib/Target/PowerPC/PPCPredicates.cpp Normal file
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@ -0,0 +1,30 @@
//===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by Chris Lattner and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the PowerPC branch predicates.
//
//===----------------------------------------------------------------------===//
#include "PPCPredicates.h"
#include <cassert>
using namespace llvm;
PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC branch opcode!");
case PPC::PRED_EQ: return PPC::PRED_NE;
case PPC::PRED_NE: return PPC::PRED_EQ;
case PPC::PRED_LT: return PPC::PRED_GE;
case PPC::PRED_GE: return PPC::PRED_LT;
case PPC::PRED_GT: return PPC::PRED_LE;
case PPC::PRED_LE: return PPC::PRED_GT;
case PPC::PRED_NU: return PPC::PRED_UN;
case PPC::PRED_UN: return PPC::PRED_NU;
}
}

39
lib/Target/PowerPC/PPCPredicates.h Normal file
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@ -0,0 +1,39 @@
//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by Chris Lattner and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the PowerPC branch predicates.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_POWERPC_PPCPREDICATES_H
#define LLVM_TARGET_POWERPC_PPCPREDICATES_H
#include "PPC.h"
namespace llvm {
namespace PPC {
/// Predicate - These are "(BI << 5) | BO" for various predicates.
enum Predicate {
PRED_ALWAYS = (0 << 5) | 20,
PRED_LT = (0 << 5) | 12,
PRED_LE = (1 << 5) | 4,
PRED_EQ = (2 << 5) | 12,
PRED_GE = (0 << 5) | 4,
PRED_GT = (1 << 5) | 12,
PRED_NE = (2 << 5) | 4,
PRED_UN = (3 << 5) | 12,
PRED_NU = (3 << 5) | 4
};
/// Invert the specified predicate. != -> ==, < -> >=.
Predicate InvertPredicate(Predicate Opcode);
}
}
#endif