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[X86] AVX512: Add writemask variants for vperm*2*
This includes assembler and codegen support (see the new tests in avx512-encodings.s and avx512-shuffle.ll). <rdar://problem/17492620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212221 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -609,7 +609,7 @@ defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
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// -- VPERM2I - 3 source operands form --
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multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
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PatFrag mem_frag, X86MemOperand x86memop,
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SDNode OpNode, ValueType OpVT> {
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SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
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let Constraints = "$src1 = $dst" in {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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@ -619,32 +619,86 @@ let Constraints = "$src1 = $dst" in {
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
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EVEX_4V;
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def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst {${mask}}|"
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"$dst {${mask}}, $src2, $src3}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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RC:$src3),
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RC:$src1)))]>,
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EVEX_4V, EVEX_K;
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let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
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def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst {${mask}} {z} |",
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"$dst {${mask}} {z}, $src2, $src3}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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RC:$src3),
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(OpVT (bitconvert
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(v16i32 immAllZerosV))))))]>,
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EVEX_4V, EVEX_KZ;
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, RC:$src2,
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(OpVT (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3))))]>, EVEX_4V;
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def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst {${mask}}|"
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"$dst {${mask}}, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)),
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RC:$src1)))]>,
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EVEX_4V, EVEX_K;
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let AddedComplexity = 10 in // Prefer over the rrkz variant
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def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst {${mask}} {z}|"
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"$dst {${mask}} {z}, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (vselect KRC:$mask,
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(OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)),
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(OpVT (bitconvert
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(v16i32 immAllZerosV))))))]>,
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EVEX_4V, EVEX_KZ;
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}
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}
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defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
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X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
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X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
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X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
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X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
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i512mem, X86VPermiv3, v16i32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
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i512mem, X86VPermiv3, v8i64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
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i512mem, X86VPermiv3, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
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i512mem, X86VPermiv3, v8f64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
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X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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X86VPermv3, v16i32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
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X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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X86VPermv3, v8i64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
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X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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X86VPermv3, v16f32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
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X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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X86VPermv3, v8f64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
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(v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
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@ -56,6 +56,16 @@ define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
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ret <8 x double> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test5m:
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; CHECK: vpermt2pd {{.* {%k[1-7]} {z}}}
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define <8 x double> @test5m(<8 x double> %a, <8 x double> %b, i8 %mask) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x double> %c, <8 x double> zeroinitializer
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ret <8 x double> %res
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}
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; CHECK-LABEL: test6:
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; CHECK: vpermq $30
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; CHECK: ret
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@ -72,6 +82,27 @@ define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
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ret <8 x i64> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test7m:
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; CHECK: vpermt2q {{.* {%k[1-7]} {z}}}
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define <8 x i64> @test7m(<8 x i64> %a, <8 x i64> %b, i8 %mask) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
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ret <8 x i64> %res
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}
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; The mem variant of vpermt2 with a writemask
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; CHECK-LABEL: test7mm:
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; CHECK: vpermt2q {{\(.*\).* {%k[1-7]} {z}}}
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define <8 x i64> @test7mm(<8 x i64> %a, <8 x i64> *%pb, i8 %mask) nounwind {
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%b = load <8 x i64>* %pb
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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%m = bitcast i8 %mask to <8 x i1>
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%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> zeroinitializer
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ret <8 x i64> %res
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}
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; CHECK-LABEL: test8:
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; CHECK: vpermt2d
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; CHECK: ret
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@ -80,6 +111,27 @@ define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
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ret <16 x i32> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test8m:
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; CHECK: vpermt2d {{.* {%k[1-7]} {z}}}
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define <16 x i32> @test8m(<16 x i32> %a, <16 x i32> %b, i16 %mask) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x i32> %c, <16 x i32> zeroinitializer
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ret <16 x i32> %res
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}
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; The mem variant of vpermt2 with a writemask
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; CHECK-LABEL: test8mm:
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; CHECK: vpermt2d {{\(.*\).* {%k[1-7]} {z}}}
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define <16 x i32> @test8mm(<16 x i32> %a, <16 x i32> *%pb, i16 %mask) nounwind {
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%b = load <16 x i32> * %pb
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x i32> %c, <16 x i32> zeroinitializer
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ret <16 x i32> %res
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}
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; CHECK-LABEL: test9:
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; CHECK: vpermt2ps
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; CHECK: ret
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@ -88,6 +140,16 @@ define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
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ret <16 x float> %c
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}
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; The reg variant of vpermt2 with a writemask
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; CHECK-LABEL: test9m:
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; CHECK: vpermt2ps {{.*}} {%k{{.}}} {z}
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define <16 x float> @test9m(<16 x float> %a, <16 x float> %b, i16 %mask) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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%m = bitcast i16 %mask to <16 x i1>
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%res = select <16 x i1> %m, <16 x float> %c, <16 x float> zeroinitializer
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ret <16 x float> %res
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}
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; CHECK-LABEL: test10:
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; CHECK: vpermt2ps (
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; CHECK: ret
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@ -3199,3 +3199,19 @@ vpcmpd $1, %zmm24, %zmm7, %k5{%k4}
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// CHECK: vpcmpuq $2,
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// CHECK: encoding: [0x62,0xf3,0xf5,0x47,0x1e,0x72,0x01,0x02]
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vpcmpuq $2, 0x40(%rdx), %zmm17, %k6{%k7}
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// CHECK: vpermi2d
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// CHECK: encoding: [0x62,0x42,0x6d,0x4b,0x76,0xd6]
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vpermi2d %zmm14, %zmm2, %zmm26 {%k3}
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// CHECK: vpermt2pd
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// CHECK: encoding: [0x62,0xf2,0xcd,0xc6,0x7f,0xf3]
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vpermt2pd %zmm3, %zmm22, %zmm6 {%k6} {z}
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// CHECK: vpermi2q
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// CHECK: encoding: [0x62,0x62,0xed,0x4b,0x76,0x54,0x58,0x02]
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vpermi2q 0x80(%rax,%rbx,2), %zmm2, %zmm26 {%k3}
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// CHECK: vpermt2d
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// CHECK: encoding: [0x62,0x32,0x4d,0xc2,0x7e,0x24,0xad,0x05,0x00,0x00,0x00]
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vpermt2d 5(,%r13,4), %zmm22, %zmm12 {%k2} {z}
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