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Add memory operand and int regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28896 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -62,6 +62,10 @@ namespace {
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode);
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bool PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode);
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};
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} // end of anonymous namespace
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@ -277,3 +281,13 @@ bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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printOperand(MI, OpNo);
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return false;
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}
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bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo);
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return false;
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}
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@ -119,6 +119,24 @@ namespace {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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SDOperand Op0;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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Select(Op0, Op);
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break;
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}
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OutOps.push_back(Op0);
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return false;
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}
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// Include the pieces autogenerated from the target description.
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#include "AlphaGenDAGISel.inc"
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@ -591,6 +591,7 @@ AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
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switch (ConstraintLetter) {
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default: break;
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case 'f':
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case 'r':
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return C_RegisterClass;
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}
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return TargetLowering::getConstraintType(ConstraintLetter);
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@ -614,6 +615,19 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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Alpha::F24, Alpha::F25, Alpha::F26,
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Alpha::F27, Alpha::F28, Alpha::F29,
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Alpha::F30, Alpha::F31, 0);
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case 'r':
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return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
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Alpha::R3 , Alpha::R4 , Alpha::R5 ,
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Alpha::R6 , Alpha::R7 , Alpha::R8 ,
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Alpha::R9 , Alpha::R10, Alpha::R11,
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Alpha::R12, Alpha::R13, Alpha::R14,
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Alpha::R15, Alpha::R16, Alpha::R17,
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Alpha::R18, Alpha::R19, Alpha::R20,
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Alpha::R21, Alpha::R22, Alpha::R23,
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Alpha::R24, Alpha::R25, Alpha::R26,
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Alpha::R27, Alpha::R28, Alpha::R29,
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Alpha::R30, Alpha::R31, 0);
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}
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}
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